/***********************************************************************
   
     machine_defs.h
   
   ***********************************************************************/

  /*************************************************************************
   *                                                                       *
   *               Copyright (C) 1993-1998 Stanford University             *
   *                                                                       *
   *  These coded instructions, statements, and computer programs contain  *
   *  unpublished proprietary information of Stanford University, and      *
   *  are protected by Federal copyright law.  They may not be disclosed   *
   *  to third parties or copied or duplicated in any form, in whole or    *
   *  in part, without the prior written consent of Stanford University.   *
   *                                                                       *
   *************************************************************************/

#ifndef __DPGCC__
#ifndef _HEADER_STACK_
#define _HEADER_STACK_
#endif
#endif

#ifndef _MACHINE_DEFS_H
#define _MACHINE_DEFS_H

/*
 * Created by: Dan Teodosiu, 07/96
 *
 * This header file defines the OS view of the MAGIC service address space
 * and of the device registers.
 *
 * The service address space addresses used by the OS are VIRTUAL addresses.
 * Depending on whether we simulate a 32 bit or a 64 bit processor,
 * the service address mappings will be different. MAGIC physical addresses
 * are 40 bits wide, so in 32 bit mode (current SimOS) we had to squeeze
 * the service address space into less address bits.
 *
 * There are two kinds of macros in this file:
 *
 *  - MAGIC definitions, pertaining to the services offered by the
 *    MAGIC node controller. All these macros start with MAGIC_...,
 *    Those definitions are further subdivided into ones which do not
 *    depend on the address mappings (such as MAGIC register numbers,
 *    error codes, etc.), and ones which do (such as the macros that help
 *    construct MAGIC PPR addresses).
 *    The current simulated MAGIC only supports doubleword accesses.
 *
 *  - devices register definitions, of the form DEV_... These defs
 *    describe the various device registers. Devices are accessed by
 *    performing uncached word (32bit) reads and writes to their registers.
 *
 * Notes:
 *    The macro SIMOS64BIT selects the 64 bit version of those definitions;
 *    by default, you get the 32 bit version. 64 bit is currently not
 *    implemented.
 *
 * Related documents:
 *  - FLASH: Physical Address Layout
 *  - FLASH: PP Software Services
 *  - SimOS to FLASH Physical Address Mapping
 *
 */


/***************************************************************************
 MAGIC defs which do not depend on the virtual -> physical address mapping
 ***************************************************************************/

/** zone numbering for service address space **/

#define MAGIC_ZONE_FRAM_ALIAS       (0+0)
#define MAGIC_ZONE_BDOOR_DEV        (16+14)        /* backdoor area for devices */
#define MAGIC_ZONE_FPROM_ALIAS      (16+15)

#ifndef SIMOS64BIT
#undef  MAGIC_ZONE_FPROM_ALIAS                /* In 32bit Simos, 0xbfc00000 maps to... */
#define MAGIC_ZONE_FPROM_ALIAS      (124)        /* ... zone 124 */
#endif

/***************************************************************************
 MAGIC defs which reflect the virtual -> physical address mapping
 ***************************************************************************/

/* auxiliary defs -- ONLY FOR INTERNAL USE IN THIS FILE */

#ifndef SIMOS64BIT     /* 32 bit address space (current SimOS version) */

/* virtual addresses for start of FPROM and FRAM */
#define FPROM_BASE _SEXT(0xbfc00000)
#define FRAM_BASE  _SEXT(0xa0000000)

#ifdef _KERNEL
#define __MAGIC_BASE                COMPAT_K1BASE /* KSEG1 */
#define __MAGIC_BASE_ACC            COMPAT_K1BASE /* still KSEG1 */
#else
#define __MAGIC_BASE                K1BASE /* KSEG1 */
#define __MAGIC_BASE_ACC            K1BASE /* still KSEG1 */
#endif
#define __MAGIC_OSPC_BASE           (K0BASE+0x1000) /* OSPC right after remap */
#define __MAGIC_OSPC_END            (K0BASE+0x2000) /* 1 page-alias for each node */

#define __MAGIC_NODE_BITS           2  /* max. 4 nodes */
#define __MAGIC_NODE_OFFS           27

#define __MAGIC_ZONE_BITS           7  /* 128 zones / node */
#define __MAGIC_ZONE_OFFS           20 /* 1MB / zone */

#define __MAGIC_REG_BITS            17
#define __MAGIC_REG_OFFS            3  /* registers are 64bit */

#define __MAGIC_PPC_SEQ_BITS        7  /* one cache line */
#define __MAGIC_PPC_SEQ_OFFS        0
#define __MAGIC_PPC_OPC_BITS        5  /* group corresponds to a 4K page */
#define __MAGIC_PPC_OPC_OFFS        __MAGIC_PPC_SEQ_BITS
#define __MAGIC_PPC_GRP_BITS        8
#define __MAGIC_PPC_GRP_OFFS        (__MAGIC_PPC_SEQ_BITS+__MAGIC_PPC_OPC_BITS)

#define __MAGIC_ZONE(node, nbits, zone)                                    \
   ( __MAGIC_BASE | ((node) << __MAGIC_NODE_OFFS)                          \
                  | ((zone) << __MAGIC_ZONE_OFFS) )
#define __MAGIC_ZONE_ACC(node, nbits, zone)                                \
   ( __MAGIC_BASE_ACC | ((node) << __MAGIC_NODE_OFFS)                      \
                      | ((zone) << __MAGIC_ZONE_OFFS) )
#define __MAGIC_ZONE_ALIAS(zone)                                           \
   ( __MAGIC_BASE | ((zone) << __MAGIC_ZONE_OFFS) )
#define __MAGIC_ZONE_ALIAS_ACC(zone)                                       \
   ( __MAGIC_BASE_ACC | ((zone) << __MAGIC_ZONE_OFFS) )
#define __MAGIC_OSPC_RANGE(node, nbits)                                    \
   ( __MAGIC_OSPC_BASE )

#define MAGIC_MAX_REMAP_PAGES       1  /* max. sz of remap area (limited
					* by OSPC in following page) */

/* offsets in bdoor zone of simulated devices (64KB each) */
#define __MAGIC_BDOOR_CLOCK_OFFS        0x00000000 /* CMOS rt clock */
#define __MAGIC_BDOOR_CNSLE_OFFS        0x00001000 /* console interface */
#define __MAGIC_BDOOR_ETHER_OFFS        0x00002000 /* ethernet controller */
#define __MAGIC_BDOOR_DISKS_OFFS        0x00010000 /* scsi disk controller */

#ifdef TORNADO
#define __MAGIC_BDOOR_GIZMO_OFFS	                                      \
    ((__MAGIC_BDOOR_DISKS_OFFS + sizeof(DevDiskRegisters)*DEV_DISK_MAX_UNIT + \
      0x1000 - 1) & ~(0x1000-1))		   /* gizmo interface */
#endif

#else /* SIMOS64BIT */ /* 64 bit address space */
not yet implemented, will not compile;
#endif /* SIMOS64BIT */

#ifdef LANGUAGE_ASSEMBLY
#define MagicRegister int
#define MAGICREGP_CAST
#else
typedef unsigned long long MagicRegister;
#define MAGICREGP_CAST (MagicRegister *)
#endif

/***************************************************************************
 definitions of the simulated devices and of various parameters
 which depend on the simulator.
 ***************************************************************************/

#define MAGIC_MAX_CPUS                32 /* max no of nodes in a simulation */
#define MAGIC_MAX_CELLS               32 /* max no of cells in a simulation */


/* needed so assembly files can include machine_defs */
#ifndef LANGUAGE_ASSEMBLY

#ifdef _KERNEL
#if defined(_MIPS3_ADDRSPACE) || defined(_K64U64)
/* Origin2000 running M-Mode assumes node size is 32bits,
 which happens to match flash's notion with nnbits=8 */
#define MAGIC_NODE_SIZE_BITS            32
#define MAGIC_NODE_OFFSET_MASK          ((1LL << MAGIC_NODE_SIZE_BITS) - 1)
/*typedef unsigned long long DevRegister;*/
typedef unsigned int DevRegister;	/*XXXblythe use 32-bit dev register*/
#else
typedef unsigned int DevRegister;
#endif
#else /* _KERNEL */
#ifdef SIM_MIPS64
#define MAGIC_NODE_SIZE_BITS            32
#define MAGIC_NODE_OFFSET_MASK          ((1LL << MAGIC_NODE_SIZE_BITS) - 1)
/*typedef unsigned long long DevRegister;*/
typedef unsigned int DevRegister;	/*XXXblythe use 32-bit dev register*/
#else
typedef unsigned int DevRegister;
#endif
#endif /* _KERNEL */

/* disk device:
 * there is currently one controller per cell. The controller
 * can be accessed through the backdoor zone of the first node
 * in the cell.
 */

#define DEV_DISK_CMD_SIZE            12
#define DEV_DISK_MAX_DMA_LENGTH      1024 /* max no of pages for one request */
#define DEV_DISK_MAX_UNIT            128  /* max disks per node. Note the disks
					   * might be attached to different
					   * controllers.
					   */

typedef struct DevDiskRegisters {
    DevRegister intr_pending;     /* r:int posted for this disk / w:ack int */
    DevRegister errnoVal;         /* status of last i/o */
    DevRegister bytesTransferred; /* bytes transferred during last i/o */

    DevRegister interruptNode;    /* node to interrupt upon completion */
    DevRegister k0Addr[DEV_DISK_MAX_DMA_LENGTH]; /* page addresses */
    DevRegister offset;           /* page offset for first page */
    DevRegister command[DEV_DISK_CMD_SIZE]; /* i/o command */

    DevRegister startIO;          /* write here causes i/o initiation */
    DevRegister doneIO;           /* tells when i/o complete */

    DevRegister filler[16];       /* filler: resize when you add new regs */
} DevDiskRegisters;

#define DEV_DISK_REGISTERS(node, nbits, unit)                         \
   ( ((volatile DevDiskRegisters*)                                    \
        (__MAGIC_ZONE(node, nbits, MAGIC_ZONE_BDOOR_DEV) +            \
         __MAGIC_BDOOR_DISKS_OFFS)) +                                 \
     (unit) )


/* console device:
 * there is currently one console per cell. The console registers
 * can be accessed through the backdoor zone of the first node
 * in the cell. The console always interrupts this node.
 */

#define DEV_CNSLE_TX_INTR            0x01 /* intr enable / state bits */
#define DEV_CNSLE_RX_INTR            0x02

typedef struct DevConsoleRegisters {
    DevRegister intr_status;      /* r: intr state / w: intr enable */
    DevRegister data;             /* r: current char / w: send char */
} DevConsoleRegisters;
 
#define DEV_CONSOLE_REGISTERS(node, nbits)                                  \
   ( ((volatile DevConsoleRegisters*)                                       \
        (__MAGIC_ZONE(node, nbits, MAGIC_ZONE_BDOOR_DEV) +                  \
         __MAGIC_BDOOR_CNSLE_OFFS)) )


/* ethernet device:
 * there is currently one ether interface per cell. The ether registers
 * can be accessed through the backdoor zone of the first node
 * in the cell. The ether interface always interrupts this node.
 */

#define DEV_ETHER_MAX_RCV_ENTRIES    64
#define DEV_ETHER_MAX_SND_ENTRIES    64
#define DEV_ETHER_MAX_SND_CHUNKS     128

#define DEV_ETHER_MAX_TRANSFER_SIZE  1800

typedef struct DevEtherRegisters {
  DevRegister etheraddr[6];       /* controller tells OS its ethernet addr */
  DevRegister numRcvEntries;      /* read by OS, indicates how many receive
				   * ring buffer entries will be used. OS must
				   * allocate a receive buffer for each of
				   * these entries */
  DevRegister numSndEntries;      /* read by OS, indicates how many send ring
				   * buffer entries will be used so it knows
				   * when to wrap its index pointer */
  DevRegister numSndChunks;       /* same as numSndEntries */

  struct {
    DevRegister pAddr;
    DevRegister maxLen;
    DevRegister len;
    DevRegister flag;         
  } rcvEntries[ DEV_ETHER_MAX_RCV_ENTRIES ];

  struct {
    DevRegister firstChunk;
    DevRegister lastChunk;
    DevRegister flag; /* triggers send */
  } sndEntries[ DEV_ETHER_MAX_SND_ENTRIES ];

  struct { 
    DevRegister pAddr;
    DevRegister len;
  } sndChunks[ DEV_ETHER_MAX_SND_CHUNKS ]; 

  /* note: sndChunks is last because we might extend the number of
   * send chunks in the future and don't want to break OS compatibility when
   * we do it */
} DevEtherRegisters;

/* values for flag field */
#define DEV_ETHER_OS_OWNED           (DevRegister)1
#define DEV_ETHER_CONTROLLER_OWNED   (DevRegister)2

#define DEV_ETHER_REGISTERS(node, nbits)                                  \
   ( ((volatile DevEtherRegisters*)                                       \
        (__MAGIC_ZONE(node, nbits, MAGIC_ZONE_BDOOR_DEV) +                \
         __MAGIC_BDOOR_ETHER_OFFS)) )


/* CMOS RT clock device:
 * This simulates a very primitive CMOS clock. This device only
 * has one register that contains the time since January 1, 1970
 * (same as the Unix gettimeofday() result).
 */

typedef struct DevClockRegisters {
  DevRegister ctime;              /* current time */
} DevClockRegisters;

#define DEV_CLOCK_REGISTERS(node, nbits)                                  \
   ( ((volatile DevClockRegisters*)                                       \
        (__MAGIC_ZONE(node, nbits, MAGIC_ZONE_BDOOR_DEV) +                \
         __MAGIC_BDOOR_CLOCK_OFFS)) )


#endif /* LANGUAGE_ASSEMBLY */


/* Interrupt bit assignments:
 *
 * There are 64 external interrupt lines coming into MAGIC. The
 * following defines show to what interrupt line each device is
 * connected.
 *
 * NOTE: when MAGIC posts an interrupt, the IEChigh register will
 * contain the bit number of the highest level interrupt pending,
 * so the bit numbers are also IEC's (Interrupt Exception Codes).
 */

#define DEV_IEC_SCSI                0x08    /* scsi disk controller */
#define DEV_IEC_ETHER               0x09    /* ether controller */
#define DEV_IEC_OSPC_LO             0x0a    /* low-priority SIPS */
#define DEV_IEC_VEC_REQ             0x0b    /* vector packet request */
#define DEV_IEC_KEYBDMOUSE          0x10    /* console */
#define DEV_IEC_DUART               0x11    /* serial line on FLASH board */
#define DEV_IEC_OSPC_HI             0x12    /* high-priority SIPS */
#define DEV_IEC_RECOVERY            0x13    /* recov int (posted by MAGIC) */
#define DEV_IEC_VEC_REPLY           0x14    /* vector packet reply */
#define DEV_IEC_MIG_REP             0x17    /* page migration hot page */
#define DEV_IEC_CLOCK               0x18    /* clock */
#define DEV_IEC_IPI                 0x20    /* inter-processor interrupt (level 0)*/
#define DEV_IEC_DEBUG               0x21    /* ??? */
#define DEV_IEC_IPI1                 0x22    /* inter-processor interrupt (level 1)*/
#define DEV_IEC_IPI2                 0x23    /* inter-processor interrupt (level 2)*/
#define DEV_IEC_PROFTIM             0x28    /* prof timer (currently unused) */
#define DEV_IEC_MAGICWARN           0x29    /* ??? */
#define DEV_IEC_MAGICERR            0x31    /* ??? */
#define DEV_IEC_POWERFAIL           0x38    /* ??? */

#define DEV_IEC_MAX                 0x3f    /* 64 bits */


/* PCI slot assignments:
 *
 * NOTE:
 * On the real system these slot assignments wouldn't be fixed (you
 * could plug a card into any slot on the I/O bus) but this isn't
 * particularly interesting to model.
 */

#define DEV_PCI_DISK_SLOT           0
#define DEV_PCI_ETHER_SLOT          1
#define DEV_PCI_CONSOLE_SLOT        2


#endif /* _MACHINE_DEFS_H */