vu.h
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/*
* Vector Unit instruction Simulation
*/
#define VU_NREG 32 /* number of VU registers per pipeline */
#define VU_NMAC 4 /* number of MAC data paths */
#define VU_WREG(r) ((r > 1) && (r < VU_NREG)) /* writtable regs */
#define VU_REG(u, r) (vu.vregs[u][r]) /* registers access */
#define VU_VCC (vu.vcc)
/*
* Selection codes
*/
#define SEL_LT 0
#define SEL_LE 1
#define SEL_EQ 2
#define SEL_NE 3
#define SEL_GE 4
#define SEL_GT 5
#define SEL_MERGE 6
#define SEL_CL 7
struct vu_state {
short vregs[VU_NMAC][VU_NREG]; /* reg file, vreg's' = short */
int vacc[VU_NMAC]; /* accumulator */
short vcc; /* condition code control */
};
struct vu_state vu;
/*
* VU instructions
*/
#define mul16( s, t) ((long)s * (long)t) /* force 32 bit product */
#define mulfs(s,t,e,d) vu_mul(s,t,e,d,0,0,1)
#define macfs(s,t,e,d) vu_mac(s,t,e,d,0,0,1)
#define mulf(s,t,d) vu_mul(s,t,0,d,0,0,0)
#define macf(s,t,d) vu_mac(s,t,0,d,0,0,0)
#define mulis(s,t,e,d) vu_mul(s,t,e,d,0,-15,1)
#define macis(s,t,e,d) vu_mac(s,t,e,d,0,-15,1)
#define muli(s,t,d) vu_mul(s,t,0,d,0,-15,0)
#define maci(s,t,d) vu_mac(s,t,0,d,0,-15,0)
#define mulus(s,t,e,d) vu_mulu(s,t,e,d,0,-15,1)
#define macus(s,t,e,d) vu_macu(s,t,e,d,0,-15,1)
#define mulu(s,t,d) vu_mulu(s,t,0,d,0,-15,0)
#define macu(s,t,d) vu_macu(s,t,0,d,0,-15,0)
#define mudls(s,t,e,d) vu_mul(s,t,e,d,1,-15,1)
#define madls(s,t,e,d) vu_mac(s,t,e,d,1,-15,1)
#define mudl(s,t,d) vu_mul(s,t,0,d,1,-15,0)
#define madl(s,t,d) vu_mac(s,t,0,d,1,-15,0)
#define mudms mulis
#define madms macis
#define mudm muli
#define madm maci
#define mudhs(s,t,e,d) vu_mul(s,t,e,d,1,15,1)
#define madhs(s,t,e,d) vu_mac(s,t,e,d,1,15,1)
#define mudh(s,t,d) vu_mul(s,t,0,d,1,15,0)
#define madh(s,t,d) vu_mac(s,t,0,d,1,15,0)
#define div(s,t,e,d) vu_div(s,t,e,d,1)
#define divh(s,t,e,d) vu_divd(s,t,e,d,1,1)
#define divl(s,t,e,d) vu_divd(s,t,e,d,0,1)
#define cmp_cl(s,t,e) vu_select(s,t,e,SEL_CL,1)
/*
* Vectorization Simulation VU register allocation
*/
#define Vzero 0 /* XXX - make sure SPECed read only reserved */
#define Vone 1 /* XXX - make sure SPECed read only reserved */
#define Vvtxo 2 /* object space vtx */
#define Vvtxci 3 /* clip space vtx integer portion */
#define Vvtxcf 4 /* clip space vtx fraction portion */
#define Vvtxs 5 /* screen space vtx */
#define Vrwh 18 /* use 20-23 as scratch */
#define Vrwl 19
/* XXX write into garbage can, simulator does not prevent a write to Vzero yet */
#define Vnull 20
#define Vdcs 22 /* device coordinate scale */
#define Vdct 23 /* device coordinate translate */
#define Vmtxi0 24 /* Matrix row0 int */
#define Vmtxf0 (Vmtxi0+1) /* Matrix row0 frac */
#define Vmtxi1 (Vmtxi0+2) /* Matrix row1 int */
#define Vmtxf1 (Vmtxi0+3) /* Matrix row1 frac */
#define Vmtxi2 (Vmtxi0+4) /* Matrix row2 int */
#define Vmtxf2 (Vmtxi0+5) /* Matrix row2 frac */
#define Vmtxi3 (Vmtxi0+6) /* Matrix row3 int */
#define Vmtxf3 (Vmtxi0+7) /* Matrix row3 frac */
/*
* function prototypes for utility routines
*/
void ftos(float, short *, short *);
void ftoi(int, short *, short *);
void stof(short, short, float *);
void vprintmtx(int r);