10/26/94
rev 11/13/94
kmh



Overview:

The Serial Interface (SI) function interfaces to the Ninitendo defined
Peripheral Interface Chip  (PIF) to read and write boot rom/ram and
game controllers from a ram inside the PIF chip.

The SI supports 4 basic functions:
1) IO reads: CPU reads of 32 bit PIF ram/rom locations.
2) IO Writes: CPU writes of 32 bits to PIF ram locations.
3) Read DMA:  64byte transfers from DRAM to pif.
4) Write DMA: 64byte transfers from pif ram to DRAM

Additionaly, the system boot address is mapped to the PIF rom address space.
Thus the SI interface to the PIF supports the initial boot process.

Operations:

The SI is a slaved to CPU requests for DMA and IO operations.
The CPU requests dma to occur between the PIF and DRAM by 
First) loading the target DRAM address to the SI_DRAM_ADDRESS register
Then) by loading the target pif address to one of 2 PIF address registers,
the specific address register indicates the specific command to perform
(write or read dma).

The CPU performs reads of the PIF memory locations by executing
an instruction from or requesting a read of 4 bytes from the
PIF address domain.

The CPU performs writes to the PIF memory by requesting write transfers
of 4 bytes of data to an address in the PIF address domain.

 SI External Control registers                 Operation
R0 SI_DRAM_ADDRESS  = 0x0480_0000       Load 24 bit DRAM target address regsiter

R1 PIF_AD_RD64B     = 0x0480_0004       Load PIF address register and request
                                        64Bytes PIF -> DRAM DMA transaction.

R4 PIF_AD_WR64B     = 0x0480_0010       Load PIF address register and request
					64Bytes DRAM -> PIF DMA transaction.

R6 SI_STATUS        = 0x0480_0018       SW visible Status Register
                                        writes to this register clear
					the SI Interrupt Flag 

 SI Internal Registers
R2 PIF_AD_WR4B      = 0x0480_0008       PIF address register for IO Write
R5 PIF_AD_RD4B      = 0x0480_0014       PIF address register for IO Read


DMA REGISTERS:

R0 Register SI_DRAM_ADDRESS:
This register is written with the target DRAM address of the
DMA. A byte address must be written to this register, the lower 2 bits
are stripped off by hardware before writing.
See restrictions on address resotution indicated below.


Reading SI_DRAM_ADDRESS will provide the current byte address for a dma in
progress. The lower 2 bits are always clear.

This register is initially loaded with the target DRAM address for the
DMA. A 64Byte dma request is split into multiple 8 byte transactions
internaly, the DRAM address which is  currently being serviced is available 
in this register.

Register R1 PIF_AD_RD64B:
Writes to this register request the 64 Byte DMA transfer from PIF to DRAM to
begin. (PIF operation Read 64 Byte)
This register is written with the byte address of the target PIF memory
location.
PIF memory has a 4 byte addressing resolution.
The lower 2 bits of the address written to this register are assumed to
be zero.

Reading this register is non-destructive and provides the byte address
last written with the lower 2 bits clear.

Register R4 PIF_AD_WR64B:
Writes to this register request the 64 Byte DMA transfer from DRAM to PIF to
begin. (PIF operation Write 64 Byte)
This register is written with the byte address of the target PIF memory
location.
PIF memory has a 4 byte addressing resolution.
The lower 2 bits of the address written to this register are assumed to
be zero.

Reading this register is non-destructive and provides the byte address
last written with the lower 2 bits clear.

IO OPERATION REGISTERS:

Internal Register R2 PIF_AD_WR4B : 
This address register is written internally by the Microprocessor
Interface in response to a CPU write request to an address mapped in the
PIF address domain.
Both io_busy and dma_busy status flags are set in the SI_STATUS Register
when an IO write is requested.

Writes to this register by the CPU are undefined.
Reads of this register are undefined.

Internal Register R5 PIF_AD_RD4B : 
This address register is written internally by the Microprocessor
interface in response to a CPU read request of an address mapped in the
PIF address domain.

Upon write to this register, a GRE internal io_busy signal is raised and the
PIF is read at the address specifed with the read data being presented to
the microprossor interface on the read_data lines. The io_busy signal is
dropped when data is available signaling the microprocessor interface to
retreave the data. The io_busy signal is duplicated in the SI_STATUS
register (io_busy).

Writes to this register by the CPU are undefined.
Reads of this register are undefined.

R6 SI STATUS :
This is a readable status register availble for software
polling and software debug. 
Any write to this register clears the si_interrupt flag visible in the
SI_STATUS register and in the RCP  interrupt cause register.
 

 Status register layout:

12         11          8   7            4      3        2                  1       0
interrupt, dma_state[3:0] ,pch_state[3:0] , dma_error, read_pending , io_busy , dma_busy

 dma_busy indicates a DMA is in progress (or an IO write operation)


 io_busy indicates an io read or write operation is in progress.

 read_pending is set when an io read is requested while a dma or io
 write is in progress. The pending read will be serviced.

 dma_error is set on overlapping dma requests
 dma_error may only cleared by power on reset.

 dma_state and pch_state are internal state machine values provided for
 status. Non-zero values indicate some activity is in progress.

 interrupt is a copy of the si_interrupt which is separately gathered in the 
 rcp interrupt cause register. 




Overlapping operations:

I/O Read operations which overlap dma activities or IO write operation
will be serviced.
This is required to support the reset exception vector read requests 
caused by the NMI to the cpu following a restart button depression.

A read request overlapping an in progress operation will raise io_busy,
set read_pending and service the read at the completion of current operation.

DMA and IO writes should not be requested when other operations are in
progress.
Software must determine if any operations are in progress prior to
issuing new requests. 
DMA and IO writes generate an si_interrupt upon completion to inform
host software that the operation has concluded.
Alternatively, SW may  poll dma_busy and io_busy held in the status register
to determine if operations are in progress.
dma_busy is set for all dma and io write operations. io_busy is set
for io read and io write operations.
Note: io read operations require the CPU to stall awaiting read response data.
Since the CPU is the only controller of this interface no interrupt is
generated and no overlaps can possibly be requested.

The DRAM address register is single buffered.
All PIF address registers resolve to the same register location which is
single buffered.

Hardware attempts to prevent errors by ignoring any requests
for DMA or IO writes (registers R0,R1,R2 and R4) when
operations are in progress.
Should overlapping operations be requested, the dma_error status flag
will be set in the SI_STATUS register. This flag is only cleared on power
on system reset.


HAZARDS;

Since IO Reads must be serviced, and since the PIF address register is
single buffered. A read operation may cause the current operation to
fail by using the PIF address specifed in the read request.
IO and DMA reads of the PIF immediatly consume this register.
DMA writes to the PIF first arbitrate for dram data before consuming the
PIF address register.



Operating Restrictions

It is required that the 64 Byte dma buffer established in DRAM for 64 Byte
transactions must be on based on 64 bit address mapping.
(i.e. the DRAM byte address bits [2:0] == 0 )

Internally the SI controller buffers only 32 bits of PIF data for DMA write
operations (PIF reads) and 64 bits for DMA read operations (writes to PIF). 
This places restrictions on the dma arbiter to place the SI at a
priority which insures dma requests will be granted and serviced withing
128 clock cylces.