I/O Subsystem Verification Plan
				(10/3/94)


A. Goals
	- To ensure that both I/O reads/writes and DMA transfers between all
	  devices (both internally and externally to RCP) work correctly
	- To verify the configuration (or initialization) for each device 
	  (if any) by executing host-based program
	- To verify that all the RCP external interfaces (i.e., R4200B, RAM, 
	  ROM, PIF, Video, Audio) are tested
	- To verify the RCP bus arbitration mechanism

B. Approach
	- Black-box testing is used:
		Treat RCP as a black box and drive all tests via C-sim program 
		and R4200B verilog model.

C. Components (refer to Jeff Smith diagram for more info)
	- There are 6 external devices to the RCP:
		RDRAM, R4200B, Video DAC, Audio DAC, Peripherals
		(i.e. cartridge), PIF
	- There are 2 internal devices in the RCP:
		RSP and RDP (CMD & SPAN DMA masters)
	- There are corresponding RCP interfaces for each of the devices 
	  mentioned above. These include RI (RDRAM I/F), 
	  MI (R4200B I/F), VI (Video I/F), AI (Audio I/F), PI (Peripheral I/F),
	  SI (Serial I/F), RSP I/F, and RDP I/F (CMD buffer & SPAN buffer).
	- There are 2 internal buses CBUS and DBUS and 6 external buses: 
	  RBUS, MBUS, VBUS, ABUS, PBUS, and SBUS.

D. Tests
	1) Config the RDRAM (via R4200B)
	    a) Configure and initialize RDRAM via writing to various RI, MI
	       registers
	    b) Coverage
		- RI logic
		- MI logic and MBUS
		- CBUS

	2) Perform IO read/write from/to the RDRAM (via R4200B)
	    a) Cases
	    	 - Test all read/write requests for different sizes
		 	- Single Read:	 1-byte, 2-byte, 3-byte, 1-word, 
		 	- Block Read:	 2-word, 4-word, 8-word
		 	- Single Write:	 1-byte, 2-byte, 3-byte, 1-word, 
		 	- Block Write:	 2-word, 4-word, 8-word
		 	- Sub-block ordered: (?)
			- Check for correct address offset in case of
			  accessing 1 byte, 2 bytes, 3 bytes, etc.
			  (Note: R4200B stores data as 64-bit word internally)
		 - Test view of each page of RDRAM and its boundaries
		 	- Ultra64 has 2 RDRAMs; each RDRAM contains 2 banks; 
		   	  each bank has 512 pages; each pages holds 2 KBytes.
		   	  There are up to 4 active pages cached in RI; can
			  have 1 page in each bank active.
	    b) Coverage
		- RI logic and RBUS
		- MI logic and MBUS 
		- CBUS

	3) Perform IO read/write from/to VI, AI, PI, and SI registers
	    a) Cases
		- CPU <-> VI reg
		- CPU <-> AI reg
		- CPU <-> PI reg
		- CPU <-> SI reg
	    a) Coverage
		- VI, AI, PI, and SI logic
		- CBUS

	4) Perform DMA transactions between 2 external devices
	    a) Cases
		- ROM    -> RDRAM
		- PIF   <-> RDRAM
		- RDRAM  -> Video
		- RDRAM  -> Audio
		- RDRAM  -> ROM (?)
		- DMA across page boundary
	    b) Coverage
		- RI, VI, AI, PI, SI logic
		- RBUS, VBUS, ABUS, PBUS, SBUS
		- CBUS, DBUS DMA logic
		- ARB

	5) Test SP
	    a) Cases
		- CPU   <-> SP registers
		- CPU   <-> SP DMEM/IMEM
		- RDRAM <-> SP DMEM 
		- RDRAM  -> SP IMEM 
	    b) Coverage
		- SP IO and DMA logic
		- CBUS, DBUS DMA
		- XBUS

	6) Test DP
	    a) Cases
		- CPU   <-> DP SMEM 
		- RDRAM <-> DP SMEM (?)
		- RDRAM  -> DP CBUF (via DP commands: Start, End, Current)
		  DMEM   -> DP CBUF
	    b) Coverage
		- DP DMA logic
		- CBUF, SMEM
		- CBUS, DBUS DMA
	
	7) Random Testing
	    a) Cases
    		- Generate multiple DMA requests to get CBUS/DBUS contention
		  and test DMA device prioritization
    		- Intermix DMA requests with IO register reads/writes to get
		  CBUS/DBUS contention; for example, while DMA transaction is
	          in progress, CPU performs IO register read of the devices
		  performing DMA as well as other devices
	    b) Coverage
		- CBUS, DBUS DMA logic
		- ARB