dpnor0021.vmd
1.21 KB
/**************************************************************/
/* Verilog module of datapath cell DPNOR0021 */
/* Designed by Lin Yang VLSI Technology Oct. 20, 90 */
/* Designed by Linda J. Xu July, 1992 */
/* */
/* The following is the port description */
/* Data ports */
/* A1 : the input port */
/* A2 : the input port */
/* ZN : the output port */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* BF : the with/without buffer flag */
/* 0 for without buffer; 1 for with buffer */
/**************************************************************/
module dpnor0021(A1, A2, ZN);
parameter WORDSIZE = 8, DELAY = 1, BF = 1;
input [WORDSIZE-1:0] A1, A2;
output [WORDSIZE-1:0] ZN;
wire [WORDSIZE-1:0] #DELAY ZN = ~(A1 | A2);
endmodule