// Copyright 1994, Rambus Inc., All Rights Reserved
// CONFIDENTIAL INFORMATION - RAMBUS INC. PROPRIETARY
// 
// Data contained herein is proprietary information of Rambus Inc.
// which shall be treated confidentially and shall not be furnished to
// third parties or made public without prior written permission by
// Rambus Inc. Rambus Inc. does not convey any license under its
// patent, copyright or maskwork rights or any rights of others.
// 
// Data contained herein is preliminary. Rambus Inc. makes no warranties,
// expressed or implied, of functionality or suitability for any purpose.
// Rambus Inc. assumes no obligation to correct any errors contained
// herein or to advise any user of this text of any correction if such be
// made.
//
// Revision 1.15  1994/11/22  23:33:33  paley
// Netlist has added fix for stopr problem.  If stopr was asserted way
// early, such as with max setup time (just after rising edge of synclk)
// the input samplers of the rac were shut down before the rclk was turned
// off, thus, causing a problem of missing data.  This was fixed by changing
// stopr to a registered version of stopr to shut off the input samplers.
//
//
//

// HDL models

`timescale 100ps/100ps

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/RAC/rCCAnal/rCCAnal.v"
// for w5 and beyond (not for rev 1.1 of w2 & v5)
module rCCAnal (up, op5, op4, op3, op2, op1, op0, sub, add, CCtlPgm, VBias, Vref, ictrlOn, slowClk, scanM_B);
output          up;
input           op5, op4, op3, op2, op1, op0;
input           sub, add, CCtlPgm, VBias, Vref, ictrlOn, slowClk, scanM_B;
 
reg     [6:0]   Tval;   // Target value to be reached
reg     [6:0]   Cval;   // current value 
reg             up;
 
wire    Okay = CCtlPgm & VBias & Vref & scanM_B;
 
always @(posedge slowClk)
    begin
        Cval[6:1]       = {op5,op4,op3,op2,op1,op0};
        Cval[0]         = 0;
        if ((Cval > 0) && (Cval < 7'b1111111))
        begin
          if (sub == 1) Cval = Cval - 1;
          else if (add == 1) Cval = Cval + 1;
        end
	#1;
        if (Tval > Cval) up = Okay;
        else up = !Okay;
    end
 
endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/RAC/rCCBiGn/rCCBiGn.v"
module rCCBiGn (VBias, pd2);
    output VBias;
    input  pd2;

assign VBias = !pd2;

endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/RAC/rISBiGn/rISBiGn.v"
module rISBiGn (VBias, pd);
    output VBias;
    input  pd;

assign VBias = !pd;

endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/RAC/rISamp/rISamp.v"
module rISamp (Q, Q_, D, CLK, VBias, Vref);
    output Q;
    output Q_;
    input D;
    input CLK;
    input VBias;
    input Vref;

    reg		x,y; 

//always @(negedge CLK) x=D;
always @(posedge CLK) y=D;
 
nand #10 i0(Q, y, Vref, VBias);
assign Q_ = ~Q;

endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/schema/resistPS/resistPS.v"
module resistPS (PLUS, MINUS);
 inout PLUS, MINUS;
 rtran N1(PLUS, MINUS);
endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/schema/vqmsry/vqmsry.v"
// This cell is identical to msr (circuit wise)
// The reason for making it a special cell is:
//  -  We need to generate SynClk with zero delay from rc for
//     all the closks to line up.
module vqmsry (Q, D, clk, clk_);
output Q;
input D, clk, clk_;

vqlatwx U7(Q, hnl_2, clk, clk_);
vqlatw U4(hnl_2, hnl_6);
tranif1 U2(D, hnl_6, clk_);
tranif0 U3(D, hnl_6, clk);
 
endmodule
 
module vqlatwx (Y, A, clk, clk_);
output Y;
input  A, clk, clk_;
reg    Yr;
 
always @ (posedge clk) Yr = A;
assign Y  = (Yr ^ (clk ^ clk_));

endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/DLL/dDLL/dDLL.v"
module dDLL (tclkDrv_, rclkDrv_, tclkBus, rclkBus,
              ByPass, TxCLK, RxCLK, Vref, PwrUp, tclkpll, rclkpll);

output	tclkDrv_, rclkDrv_, tclkBus, rclkBus;
input	ByPass, TxCLK, RxCLK, Vref, PwrUp, tclkpll, rclkpll;

integer xr, xt, yr, yt;
reg     sc, tc, Okay, scr, tcr;
event   St_rclk, St_tclk;
 
initial
begin
        sc = 0;
        tc = 0;
        xr = 0;
        xt = 0;
        yr = 0;
        yt = 0;
        Okay = 0;
// Make this interval 64 tester cycle long
	#1280;
//      #160;
        Okay = 1;
end
 
always @(posedge PwrUp)
	begin
	Okay = 0;
	#1280;
	Okay = 1;
	end

initial @(negedge RxCLK)
         begin
          yr = $stime;
          @(negedge RxCLK)
           ->St_rclk;
         end
 
initial @(negedge TxCLK)
         begin
          yt = $stime;
          @(negedge RxCLK)
           ->St_tclk;
         end
 
always @(St_rclk)
        while (1)
         begin
          xr = yr;
          yr = $stime;
          sc = 0;
          sc = # ((yr-xr)/2) 1;
          @(negedge RxCLK);
         end
 
always @(St_tclk)
        while (1)
         begin
          xt = yt;
          yt = $stime;
          `ifdef RSIMCLK
            // reduce offset between tclk and rclk for rsim
            tc <= # (((yt-xt)/4) - 9) 1;
            tc <= # ((3*(yt-xt)/4) - 9) 0;
          `else
            // normal offset between tclk and rclk for verilog
            tc <= # (((yt-xt)/4) - 0) 1;
            tc <= # ((3*(yt-xt)/4) - 0) 0;
          `endif
          @(negedge TxCLK);
         end

assign	rclkDrv_ = (Okay == 1) ? (!sc & Vref & PwrUp & !ByPass) : ('bx);
assign	tclkDrv_ = (Okay == 1) ? (!tc & Vref & PwrUp & !ByPass) : ('bx);

assign  rclkBus =  RxCLK & ByPass;
not     #10 i0(tclkBus,rclkBus);

endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/schema/capN/capN.v"
module capN (PLUS, MINUS);
    inout PLUS;
    inout MINUS;
endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/schema/vqcxfr/vqcxfr.v"
module vqcxfr (D, GN, GP, S);
 output D;
 input  S;
 input GN, GP;
 wire T;
 assign T = GP ^ (1'bx || (GN ^ GP));
 nmos N1(D, S, T);
endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/schema/vqlatw/vqlatw.v"
module vqlatw (Y, A);
output Y;
inout A;

not #1                i0(Y, A);
not    (weak1, weak0) i1(A, Y);

endmodule



// End HDL models


module vqao21 (Y, A1, A2, B);
output Y;
input A1, A2, B;
supply1 vddA;
supply0 gndR;
supply1 vddR;
tranif0 P3(hnl_0, vddR, B);
tranif0 P1(Y, hnl_0, A1);
tranif0 P2(Y, hnl_0, A2);
tranif1 N1(Y, hnl_1, A1);
tranif1 N2(hnl_1, gndR, A2);
tranif1 N3(Y, gndR, B);
endmodule

module vqmsrse (Q, D, clk, clk_, de, de_, hold, hold_, se, se_, si);
output Q;
input D, clk, clk_, de, de_, hold, hold_, se, se_, si;
supply1 vddA;
supply0 gndR;
supply1 vddR;
not #(0) U31(hnl_2, Q);
not #(0) U45(hnl_3, hnl_2);
vqlatw U30(Q, hnl_4);
vqlatw U28(hnl_5, hnl_6);
vqcxfr U29(hnl_4, clk, clk_, hnl_5);
vqcxfr U26(sh, se, se_, si);
vqcxfr U25(sh, de, de_, D);
vqcxfr U24(sh, hold, hold_, hnl_3);
vqcxfr U27(hnl_6, clk_, clk, sh);
endmodule

module vqmx02 (out, a, b, sa, sb);
output out;
input a, b, sa, sb;
supply1 vddA;
supply0 gndR;
supply1 vddR;
not #(0) U3(out, hnl_7);
vqcxfr U1(hnl_7, sa, sb, a);
vqcxfr U2(hnl_7, sb, sa, b);
endmodule

module vqmsrs (Q, D, clk, clk_, se, se_, si);
output Q;
input D, clk, clk_, se, se_, si;
supply1 vddA;
supply0 gndR;
supply1 vddR;
vqlatw U7(Q, hnl_8);
vqlatw U4(hnl_9, hnl_10);
vqcxfr U5(hnl_8, clk, clk_, hnl_9);
vqcxfr U2(hnl_10, clk_, clk, sh);
vqcxfr U14(sh, se_, se, D);
vqcxfr U21(sh, se, se_, si);
endmodule

module rBIST (BISTFlag, brd_1_, brd_0_, ionbist, iotest, so, BISTMode, IOSTMode, RD_1_, RD_0_, Reset, SynClk, scanM_, se, si_);
output BISTFlag, brd_1_, brd_0_, ionbist, iotest, so;
input BISTMode, IOSTMode, RD_1_, RD_0_, Reset, SynClk, scanM_, se, si_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
vqao21 U64(brd_1_, hnl_11, hnl_12, iotest);
vqmsrse I122(hnl_13, hnl_14, SynClk, hnl_15, cnt84, hnl_16, hnl_17, hnl_18, hnl_19, rstP_, gndR);
vqmsrse I76(hnl_20, hnl_21, SynClk, hnl_15, cnt82, hnl_22, hnl_23, hnl_24, hnl_19, rstP_, gndR);
nand #(0) U63(hnl_11, hnl_25, bit2_, hnl_26, IOSTM_);
nand #(0) U116(hnl_27, hnl_21, hnl_16, hnl_22, hnl_19);
nor #(0) U88(hnl_14, hnl_28, hnl_29, hnl_30);
nor #(0) U70(cnt84, hnl_31, IOSTMode, hnl_32);
nor #(0) U86(hnl_21, hnl_33, hnl_34);
nor #(0) U141(brd_0_, brd_1_, iotest);
nor #(0) U138(iotest, bist, IOSTM_);
nor #(0) U20(hnl_35, hnl_36, hnl_37);
nor #(0) U26(hnl_38, hnl_36, hnl_5);
nor #(0) U33(hnl_39, hnl_36, hnl_2);
nor #(0) U61(hnl_26, bit4, bit6);
nor #(0) U60(hnl_25, bit3, bit5);
nor #(0) U62(hnl_40, bit4_, bit6_);
nor #(0) U78(cnt82, hnl_41, hnl_32);
nor #(0) U69(hnl_17, hnl_19, cnt84);
nor #(0) U82(hnl_23, hnl_19, cnt82);
nor #(0) U89(hnl_30, hnl_42, hnl_20);
nand #(0) U18(hnl_36, bit0, bit1, bit2);
nand #(0) U31(hnl_2, bit3, bit4, bit5);
nand #(0) U68(hnl_31, bit0_, bit1_, bit2);
nand #(0) U67(hnl_41, bit0_, bit1, bit2_);
nand #(0) U50(hnl_43, BISTMode, hnl_44, Reset);
nand #(0) U137(ionbist, bist_, IOSTM_);
nand #(0) U140(IOSTM_, IOSTMode, Reset);
nand #(0) U142(hnl_12, IOSTMode, bit6_);
nand #(0) U14(hnl_45, bit0, bit1);
nand #(0) U28(hnl_5, bit3, bit4);
nand #(0) U66(hnl_32, hnl_25, hnl_40);
nand #(0) U55(rstP_, hnl_46, Reset);
vqmx02 I93(hnl_47, vddR, bit0, bist_, bist);
vqmx02 I94(hnl_48, vddR, hnl_49, bist_, bist);
vqmx02 I95(hnl_50, vddR, hnl_51, bist_, bist);
vqmx02 I96(hnl_52, vddR, hnl_53, bist_, bist);
vqmx02 I97(hnl_54, vddR, hnl_55, bist_, bist);
vqmx02 I98(hnl_56, vddR, hnl_57, bist_, bist);
vqmx02 I99(hnl_58, vddR, hnl_59, bist_, bist);
vqmx02 I129(hnl_49, bit1, bit1_, bit0_, bit0);
vqmx02 I128(hnl_51, bit2, bit2_, hnl_45, hnl_60);
vqmx02 I127(hnl_53, bit3, hnl_37, hnl_36, hnl_61);
vqmx02 I126(hnl_55, bit4, bit4_, hnl_62, hnl_35);
vqmx02 I125(hnl_57, bit5, hnl_63, hnl_64, hnl_38);
vqmx02 I1(hnl_59, bit6, bit6_, hnl_65, hnl_39);
vqmx02 I119(hnl_66, hnl_13, hnl_67, scanM_, hnl_42);
vqmx02 I113(hnl_68, hnl_69, gndR, rstP_, hnl_19);
vqmx02 I112(hnl_69, cnt84, hnl_43, bist, bist_);
vqmsrs I117(hnl_67, hnl_27, hnl_15, SynClk, se, se_, bit6);
vqmsrs I8(bit0, hnl_47, hnl_15, SynClk, se, se_, hnl_70);
vqmsrs I41(bit1, hnl_48, hnl_15, SynClk, se, se_, bit0);
vqmsrs I40(bit2, hnl_50, hnl_15, SynClk, se, se_, bit1);
vqmsrs I39(bit3, hnl_52, hnl_15, SynClk, se, se_, bit2);
vqmsrs I38(bit4, hnl_54, hnl_15, SynClk, se, se_, bit3);
vqmsrs I37(bit5, hnl_56, hnl_15, SynClk, se, se_, bit4);
vqmsrs I35(bit6, hnl_58, hnl_15, SynClk, se, se_, bit5);
vqmsrs I91(hnl_70, BISTMode, hnl_15, SynClk, se, se_, bist);
vqmsrs BM(hnl_71, hnl_72, hnl_15, SynClk, se, se_, hnl_73);
not #(0) U145(hnl_74, hnl_75);
not #(0) U144(hnl_75, si_);
not #(0) U136(so, hnl_76);
not #(0) U135(hnl_76, hnl_67);
not #(0) U134(hnl_73, hnl_74);
not #(0) U133(hnl_34, hnl_77);
not #(0) U132(hnl_77, RD_0_);
not #(0) U131(hnl_29, hnl_78);
not #(0) U130(hnl_78, RD_1_);
not #(0) U121(BISTFlag, hnl_66);
not #(0) U109(se_, se);
not #(0) U44(hnl_15, SynClk);
not #(0) U30(bit6_, bit6);
not #(0) U24(hnl_63, bit5);
not #(0) U22(bit4_, bit4);
not #(0) U16(hnl_37, bit3);
not #(0) U12(bit2_, bit2);
not #(0) U9(bit0_, bit0);
not #(0) U11(bit1_, bit1);
not #(0) U15(hnl_60, hnl_45);
not #(0) U19(hnl_61, hnl_36);
not #(0) U34(hnl_65, hnl_39);
not #(0) U27(hnl_64, hnl_38);
not #(0) U23(hnl_62, hnl_35);
not #(0) U81(hnl_16, cnt84);
not #(0) U80(hnl_22, cnt82);
not #(0) U79(hnl_18, hnl_17);
not #(0) U83(hnl_24, hnl_23);
not #(0) U87(hnl_28, hnl_34);
not #(0) U85(hnl_33, hnl_29);
not #(0) U120(hnl_42, scanM_);
not #(0) U56(hnl_19, rstP_);
not #(0) U114(hnl_72, hnl_68);
not #(0) U57(hnl_46, BISTMode);
not #(0) U92(hnl_44, hnl_70);
not #(0) U49(bist_, hnl_71);
not #(0) U123(bist, bist_);
endmodule

module rESDpwr ();
supply1 vddA;
supply0 gndR;
supply1 vddR;
tranif0 P5(gndR, vddA, vddA);
tranif0 P2(gndR, vddR, vddR);
tranif1 N1(vddR, gndR, gndR);
tranif1 N7(vddA, gndR, gndR);
endmodule

module vqlatch (Q_, D, clk, clk_);
output Q_;
input D, clk, clk_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
vqlatw U6(Q_, hnl_8);
vqcxfr U5(hnl_8, clk, clk_, D);
endmodule

module rPrsclr (IctrlLd, ictrlOn, preSlowClk, so, CCtlLd, SynClk, pd, reset, se, si);
output IctrlLd, ictrlOn, preSlowClk, so;
input CCtlLd, SynClk, pd, reset, se, si;
supply1 vddA;
supply0 gndR;
supply1 vddR;
nor #(0) U72(hnl_79, hnl_80, hnl_81, hnl_82);
vqlatch I55(ion, c31_, SynClk, SynClkL_);
vqmsrs I58(hnl_83, CCtlLd, SynClkL_, SynClk, se, se_, hnl_84);
vqmsrs Q3(hnl_85, hnl_86, SynClkL_, SynClk, se, se_, hnl_82);
vqmsrs Q2(hnl_82, hnl_87, SynClkL_, SynClk, se, se_, hnl_81);
vqmsrs Q4(hnl_84, hnl_88, SynClkL_, SynClk, se, se_, hnl_85);
vqmsrs Q1(hnl_81, hnl_89, SynClkL_, SynClk, se, se_, hnl_80);
vqmsrs Q0(hnl_80, hnl_90, SynClkL_, SynClk, se, se_, si);
nor #(0) U73(hnl_91, hnl_84, hnl_85);
nor #(0) U71(hnl_90, hnl_80, reset);
nor #(0) U43(hnl_92, hnl_93, hnl_94);
nand #(0) U46(preSlowClk, SynClk, hnl_91, hnl_79);
nand #(0) U42(hnl_94, hnl_80, hnl_81, hnl_82);
nand #(0) U35(hnl_95, hnl_82, hnl_11);
nand #(0) U36(hnl_93, hnl_85, hnl_11);
nand #(0) U37(hnl_96, hnl_84, hnl_11);
nand #(0) U34(hnl_65, hnl_81, hnl_11);
nand #(0) U69(hnl_17, ion, hnl_31);
nand #(0) U45(c31_, hnl_79, hnl_91);
nand #(0) U39(hnl_97, hnl_81, hnl_80);
vqmx02 I32(hnl_88, hnl_96, hnl_84, hnl_15, hnl_92);
vqmx02 I31(hnl_86, hnl_93, hnl_85, hnl_94, hnl_98);
vqmx02 I30(hnl_87, hnl_95, hnl_82, hnl_97, hnl_99);
vqmx02 I29(hnl_89, hnl_65, hnl_81, hnl_100, hnl_80);
not #(0) U61(hnl_26, hnl_83);
not #(0) U78(IctrlLd, hnl_26);
not #(0) U70(ictrlOn, hnl_17);
not #(0) U68(hnl_31, pd);
not #(0) U56(so, hnl_26);
not #(0) U44(hnl_15, hnl_92);
not #(0) U41(hnl_98, hnl_94);
not #(0) U40(hnl_99, hnl_97);
not #(0) U38(hnl_100, hnl_80);
not #(0) U27(se_, se);
not #(0) U63(hnl_11, reset);
not #(0) U10(SynClkL_, SynClk);
endmodule

module rESDClk (pad);
inout pad;
supply1 vddA;
supply0 gndR;
supply1 vddR;
tranif1 N33(pad, gndR, gndR);
tranif0 P34(pad, vddR, vddR);
endmodule

module rPreLR (bcsint_3_, bcsint_2_, bcsint_1_, bcsint_0_, bdsint_3_, bdsint_2_, bdsint_1_, bdsint_0_, rcsint_3_, rcsint_2_, rcsint_1_, rcsint_0_, rdsint_3_, rdsint_2_, rdsint_1_, rdsint_0_,
BCSel_3_, BCSel_2_, BCSel_1_, BCSel_0_, BDSel_3_, BDSel_2_, BDSel_1_, BDSel_0_, RCSel_3_, RCSel_2_, RCSel_1_, RCSel_0_, RDSel_3_, RDSel_2_, RDSel_1_, RDSel_0_, bist);
output bcsint_3_, bcsint_2_, bcsint_1_, bcsint_0_, bdsint_3_, bdsint_2_, bdsint_1_, bdsint_0_, rcsint_3_, rcsint_2_, rcsint_1_, rcsint_0_, rdsint_3_, rdsint_2_, rdsint_1_, rdsint_0_;
input BCSel_3_, BCSel_2_, BCSel_1_, BCSel_0_, BDSel_3_, BDSel_2_, BDSel_1_, BDSel_0_, RCSel_3_, RCSel_2_, RCSel_1_, RCSel_0_, RDSel_3_, RDSel_2_, RDSel_1_, RDSel_0_, bist;
supply1 vddA;
supply0 gndR;
supply1 vddR;
nor #(0) U95(hnl_101, RCSel_2_, bist);
nor #(0) U19(hnl_61, RDSel_2_, bist);
nor #(0) U15(hnl_60, BDSel_0_, bist);
nor #(0) U7(hnl_102, BCSel_0_, bist);
not #(0) U103(rcsint_2_, hnl_101);
not #(0) U102(rcsint_3_, hnl_103);
not #(0) U98(rcsint_0_, hnl_104);
not #(0) U96(rcsint_1_, hnl_105);
not #(0) U25(bistb, bist);
not #(0) U24(rdsint_0_, hnl_62);
not #(0) U22(rdsint_1_, hnl_106);
not #(0) U20(rdsint_2_, hnl_61);
not #(0) U18(rdsint_3_, hnl_107);
not #(0) U16(bdsint_0_, hnl_60);
not #(0) U14(bdsint_1_, hnl_108);
not #(0) U12(bdsint_2_, hnl_109);
not #(0) U10(bdsint_3_, hnl_110);
not #(0) U8(bcsint_0_, hnl_102);
not #(0) U6(bcsint_1_, hnl_111);
not #(0) U4(bcsint_2_, hnl_112);
not #(0) U2(bcsint_3_, hnl_113);
nand #(0) U104(hnl_104, RCSel_0_, bistb);
nand #(0) U100(hnl_103, RCSel_3_, bistb);
nand #(0) U99(hnl_105, RCSel_1_, bistb);
nand #(0) U23(hnl_62, RDSel_0_, bistb);
nand #(0) U21(hnl_106, RDSel_1_, bistb);
nand #(0) U17(hnl_107, RDSel_3_, bistb);
nand #(0) U13(hnl_108, BDSel_1_, bistb);
nand #(0) U11(hnl_109, BDSel_2_, bistb);
nand #(0) U9(hnl_110, BDSel_3_, bistb);
nand #(0) U5(hnl_111, BCSel_1_, bistb);
nand #(0) U3(hnl_112, BCSel_2_, bistb);
nand #(0) U1(hnl_113, BCSel_3_, bistb);
endmodule

module rzerboB (Q, Qb, D);
output Q, Qb;
input D;
supply1 vddA;
supply0 gndR;
supply1 vddR;
not #(0) U2(Q, outa);
not #(0) U4(outc, outb);
not #(0) U1(outa, D);
not #(0) U3(outb, D);
not #(0) U5(Qb, outc);
endmodule

module ppoint (pp);
inout pp;
supply1 vddA;
supply0 gndR;
supply1 vddR;
endmodule

module rLdREn (ldBC, ldBD, ldBE, rEn, rEnC, so, BCSel_3_, BCSel_2_, BCSel_1_, BCSel_0_, BDSel_3_, BDSel_2_, BDSel_1_, BDSel_0_, BESel_3_, BESel_2_, BESel_1_, BESel_0_, RCSel_3_, RCSel_2_, RCSel_1_,
RCSel_0_, REnSel_3_, REnSel_2_, REnSel_1_, REnSel_0_, ldEn, samplse, samplse_, sclk, se, si);
output ldBC, ldBD, ldBE, rEn, rEnC, so;
input BCSel_3_, BCSel_2_, BCSel_1_, BCSel_0_, BDSel_3_, BDSel_2_, BDSel_1_, BDSel_0_, BESel_3_, BESel_2_, BESel_1_, BESel_0_, RCSel_3_, RCSel_2_, RCSel_1_, RCSel_0_, REnSel_3_, REnSel_2_, REnSel_1_,
REnSel_0_, ldEn, samplse, samplse_, sclk, se, si;
supply1 vddA;
supply0 gndR;
supply1 vddR;
rzerboB BZS(sclkL, sclkL_, sclk);
ppoint I88(sclkL_);
ppoint I87(sclkL);
nand #(0) U45(hnl_3, ldEn, hnl_114);
nand #(0) U69(hnl_17, ldEn, hnl_115);
nand #(0) U63(hnl_11, ldEn, hnl_116);
nor #(0) U89(hnl_30, hnl_15, hnl_117);
nor #(0) U34(hnl_65, hnl_15, hnl_118);
nor #(0) U31(hnl_2, hnl_15, hnl_94);
nor #(0) U64(hnl_119, hnl_15, hnl_120);
nor #(0) U59(hnl_121, hnl_15, hnl_96);
vqmsrs I98(hnl_122, RCSel_3_, sclkL, sclkL_, samplse_, samplse, hnl_30);
vqmsrs I95(hnl_123, RCSel_2_, sclkL, sclkL_, samplse_, samplse, hnl_122);
vqmsrs I92(rEnC, RCSel_0_, sclkL, sclkL_, samplse_, samplse, hnl_124);
vqmsrs I90(hnl_124, RCSel_1_, sclkL, sclkL_, samplse_, samplse, hnl_123);
vqmsrs I23(hnl_125, REnSel_1_, sclkL, sclkL_, samplse_, samplse, hnl_126);
vqmsrs I27(hnl_127, REnSel_3_, sclkL, sclkL_, samplse_, samplse, hnl_65);
vqmsrs I47(hnl_128, BESel_3_, sclkL, sclkL_, samplse_, samplse, hnl_121);
vqmsrs I11(hnl_129, BDSel_2_, sclkL, sclkL_, samplse_, samplse, hnl_130);
vqmsrs I10(hnl_130, BDSel_3_, sclkL, sclkL_, samplse_, samplse, hnl_2);
vqmsrs I48(hnl_131, BESel_2_, sclkL, sclkL_, samplse_, samplse, hnl_128);
vqmsrs I74(hnl_132, BCSel_3_, sclkL, sclkL_, samplse_, samplse, hnl_119);
vqmsrs I13(hnl_133, BDSel_1_, sclkL, sclkL_, samplse_, samplse, hnl_129);
vqmsrs I26(hnl_126, REnSel_2_, sclkL, sclkL_, samplse_, samplse, hnl_127);
vqmsrs I73(hnl_134, BCSel_2_, sclkL, sclkL_, samplse_, samplse, hnl_132);
vqmsrs I67(hnl_135, BCSel_1_, sclkL, sclkL_, samplse_, samplse, hnl_134);
vqmsrs I61(hnl_136, BESel_1_, sclkL, sclkL_, samplse_, samplse, hnl_131);
vqmsrs I25(rEn, REnSel_0_, sclkL, sclkL_, samplse_, samplse, hnl_125);
vqmsrs I54(hnl_116, BESel_0_, sclkL, sclkL_, samplse_, samplse, hnl_136);
vqmsrs I43(hnl_114, BDSel_0_, sclkL, sclkL_, samplse_, samplse, hnl_133);
vqmsrs I68(hnl_115, BCSel_0_, sclkL, sclkL_, samplse_, samplse, hnl_135);
not #(0) U97(hnl_118, rEnC);
not #(0) U96(hnl_117, si);
not #(0) U44(hnl_15, se);
not #(0) U42(hnl_94, rEn);
not #(0) U65(so, hnl_32);
not #(0) U37(hnl_96, hnl_114);
not #(0) U66(hnl_32, hnl_115);
not #(0) U58(hnl_120, hnl_116);
not #(0) U78(ldBD, hnl_3);
not #(0) U77(ldBE, hnl_11);
not #(0) U76(ldBC, hnl_17);
endmodule

module vqmsr (Q, D, clk, clk_);
output Q;
input D, clk, clk_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
vqlatw U10(Q, hnl_137);
vqlatw U8(hnl_138, hnl_139);
vqcxfr U6(hnl_137, clk, clk_, hnl_138);
vqcxfr U7(hnl_139, clk_, clk, D);
endmodule

module rDiv (fd, smpl, smpl_, syncout, PhStall, Reset, Syncin, rclkL, rclkL_);
output fd, smpl, smpl_, syncout;
input PhStall, Reset, Syncin, rclkL, rclkL_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
not #(0) U15(smpl, smpl_);
nand #(1) U14(smpl_, syncout, hnl_81);
tranif1 N37(hnl_140, gndR, hnl_141);
vqcxfr U36(hnl_140, hnl_142, hnl_141, hnl_143);
vqmsry Q0(syncout, fd, rclkL, rclkL_);
nand #(0) U33(hnl_39, hnl_144, hnl_65);
nand #(0) U29(fd, hnl_39, hnl_81);
vqmsr Q1(hnl_81, Syncin, rclkL, rclkL_);
vqmsr S3(hnl_143, hnl_145, syncout, hnl_146);
vqmsr S2(hnl_145, PhStall, syncout, hnl_146);
vqmsr S4(hnl_141, hnl_143, rclkL, rclkL_);
vqmsr S7(hnl_144, hnl_140, rclkL, rclkL_);
not #(0) S1(hnl_146, syncout);
not #(0) S5(hnl_142, hnl_141);
not #(0) U34(hnl_65, Reset);
endmodule

module vqmxfr (out, a, b, sa, sb);
output out;
input a, b, sa, sb;
supply1 vddA;
supply0 gndR;
supply1 vddR;
vqcxfr U2(out, sb, sa, b);
vqcxfr U1(out, sa, sb, a);
endmodule

module rClks2 (SCANM_, SynClk, SynClkFd, Synint, samplse, samplse_, se, slowClk_, PhStall, Reset, SCANEn, SCANMode, SynClkIn, preSlowClk, r2s, r2s_);
output SCANM_, SynClk, SynClkFd, Synint, samplse, samplse_, se, slowClk_;
input PhStall, Reset, SCANEn, SCANMode, SynClkIn, preSlowClk, r2s, r2s_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
rDiv D(hnl_147, hnl_148, hnl_149, sy4, PhStall, Reset, SynClkIn, r2s, r2s_);
nand #(1) U145(hnl_74, SCANMode, SCANEn);
vqmsry I298(SynClkFd, hnl_147, r2s, r2s_);
not #(0) U359(scanSlow_, r2s);
not #(0) U367(scanSlow, scanSlow_);
not #(0) U357(slowClk_, slow2);
not #(0) U358(slow2, slow1);
not #(0) U336(scanSync_, r2s_);
not #(0) U368(scanSync, scanSync_);
not #(0) U342(Synint, sy6);
not #(0) U347(sy6, sy5);
not #(0) U341(SynClk, sy6x);
not #(0) U344(sy6x, sy5x);
not #(0) U362(sloc1, preSlowClk);
not #(0) U311(hnl_150, hnl_151);
not #(0) U98(hnl_152, hnl_153);
not #(0) U293(samplse_, hnl_152);
not #(0) U310(samplse, hnl_150);
not #(0) U93(hnl_154, se);
not #(0) U144(se, hnl_74);
not #(0) U147(SCANM_, SCANMode);
vqmxfr I361(slow1, sloc1, scanSlow, SCANM_, SCANMode);
vqmxfr I340(sy5, sy4, scanSync, SCANM_, SCANMode);
vqmxfr I339(sy5x, sy4, gndR, SCANM_, SCANMode);
vqmxfr I309(hnl_151, hnl_148, hnl_154, SCANM_, SCANMode);
vqmxfr I251(hnl_153, hnl_149, se, SCANM_, SCANMode);
endmodule

module rClks (SCANM_, SynClk, SynClkFd, Synint, pd, pd2, rclk, rclkpll, samplse, samplse_, sclk, se, slowClk_, tclk, tclkpll, ByPSel, ByPass, PhStall, PwrUp, Reset, SCANClk, SCANEn, SCANMode, StopR,
StopT, SynClkIn, preSlowClk, rclkASIC, rclkBus, rclkDrv_, tclkASIC, tclkBus, tclkDrv_);
output SCANM_, SynClk, SynClkFd, Synint, pd, pd2, rclk, rclkpll, samplse, samplse_, sclk, se, slowClk_, tclk, tclkpll;
input ByPSel, ByPass, PhStall, PwrUp, Reset, SCANClk, SCANEn, SCANMode, StopR, StopT, SynClkIn, preSlowClk, rclkASIC, rclkBus, rclkDrv_, tclkASIC, tclkBus, tclkDrv_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
rzerboB I587(r2s, r2s_, r0);
rClks2 CK2(SCANM_, SynClk, SynClkFd, Synint, samplse, samplse_, se, slowClk_, PhStall, Reset, SCANEn, SCANMode, SynClkIn, preSlowClk, r2s, r2s_);
nor #(0) U409(hnl_155, ByPass, SCANMode);
nand #(0) U500(hnl_156, hnl_157, hnl_158, hnl_159);
vqmx02 I540(hnl_160, tclkASIC, tclkBus, ByPSel_, ByPSel);
vqmx02 I542(hnl_161, rclkASIC, rclkBus, ByPSel_, ByPSel);
nand #(0) U401(pd, hnl_162, PwrUp);
nand #(0) U504(hnl_163, hnl_157, hnl_158);
nand #(0) U431(hnl_164, hnl_159, hnl_158);
not #(0) U615(pd2, PwrUp);
not #(0) U406(ByPSel_, ByPSel);
not #(0) U593(SCANClk_, SCANClk);
not #(0) U592(SCANClkT, SCANClk_);
not #(0) U501(hnl_165, hnl_156);
not #(0) U400(hnl_162, hnl_157);
not #(0) U506(Synint_, Synint);
not #(0) U502(hnl_166, hnl_163);
not #(0) U425(hnl_167, hnl_164);
not #(0) U564(r4, r3);
not #(0) U554(rclk, r4);
not #(0) U567(t2, t1);
not #(0) U581(tclk, t4);
not #(0) U583(hnl_168, tl4);
not #(0) U577(hnl_169, tl4);
not #(0) U611(hnl_170, gndR);
not #(0) U610(hnl_171, gndR);
not #(0) U605(hnl_172, gndR);
not #(0) U598(hnl_173, gndR);
not #(0) U584(r0, rout);
not #(0) U585(r1, r0);
not #(0) U589(t0, tout);
not #(0) U590(t1, t0);
not #(0) U575(tl2, t1);
not #(0) U568(tl4, tl3);
not #(0) U607(tclkpll, tl4);
not #(0) U578(tclkpld, gndR);
not #(0) U579(t4, t3);
not #(0) U553(s2, r1);
not #(0) U559(sclk, s4);
not #(0) U563(s4, s3);
not #(0) U550(r2, r1);
not #(0) U561(sl2, r1);
not #(0) U597(hnl_174, sl4);
not #(0) U547(hnl_175, sl4);
not #(0) U552(hnl_176, sl4);
not #(0) U606(sl4, sl3);
not #(0) U555(rclkpll, sl4);
not #(0) U53(hnl_158, SCANMode);
not #(0) U410(hnl_177, hnl_155);
vqmxfr I548(r3, r2, gndR, hnl_163, hnl_166);
vqmxfr I566(s3, s2, gndR, hnl_156, hnl_165);
vqmxfr I574(t3, t2, vddR, hnl_164, hnl_167);
vqmxfr I594(scanR, hnl_161, SCANClk_, hnl_158, SCANMode);
vqmxfr I586(rout, rclkDrv_, scanR, hnl_155, hnl_177);
vqmxfr I588(tout, tclkDrv_, scanT, hnl_155, hnl_177);
vqmxfr I591(scanT, hnl_160, SCANClkT, hnl_158, SCANMode);
vqmxfr I582(tl3, tl2, vddR, vddR, gndR);
vqmxfr I549(sl3, sl2, gndR, vddR, gndR);
vqmsr U4(hnl_159, StopT, Synint, Synint_);
vqmsr I503(hnl_157, StopR, Synint, Synint_);
endmodule

module rRACC (SCANM_, SynClk, SynClkFd, Synint, ictrlLd, ictrlOn, ldBC, ldBD, ldBE, pd, pd2, rEn, rEnC, rclk, sclk, se, slowClk_, so, tclk, BCSel_3_, BCSel_2_, BCSel_1_, BCSel_0_, BDSel_3_, BDSel_2_,
BDSel_1_, BDSel_0_, BESel_3_, BESel_2_, BESel_1_, BESel_0_, BusClk, ByPSel, ByPass, CCtlLd, PhStall, PwrUp, RCSel_3_, RCSel_2_, RCSel_1_, RCSel_0_, REnSel_3_, REnSel_2_, REnSel_1_, REnSel_0_, Reset,
SCANClk, SCANEn, SCANMode, StopR, StopT, SynClkIn, Vref, bist, ldEn, rclkASIC, si, tclkASIC);
output SCANM_, SynClk, SynClkFd, Synint, ictrlLd, ictrlOn, ldBC, ldBD, ldBE, pd, pd2, rEn, rEnC, rclk, sclk, se, slowClk_, so, tclk;
input BCSel_3_, BCSel_2_, BCSel_1_, BCSel_0_, BDSel_3_, BDSel_2_, BDSel_1_, BDSel_0_, BESel_3_, BESel_2_, BESel_1_, BESel_0_, BusClk, ByPSel, ByPass, CCtlLd, PhStall, PwrUp, RCSel_3_, RCSel_2_,
RCSel_1_, RCSel_0_, REnSel_3_, REnSel_2_, REnSel_1_, REnSel_0_, Reset, SCANClk, SCANEn, SCANMode, StopR, StopT, SynClkIn, Vref, bist, ldEn, rclkASIC, si, tclkASIC;
supply1 vddA;
supply0 gndR;
supply1 vddR;
capN C1(vddR, gndR);
rESDpwr EP();
rPrsclr P(ictrlLd, ictrlOn, preSlowClk, so, CCtlLd, Synint, pd, Reset, se, hnl_178);
dDLL L(tclkDrv_, rclkDrv_, tclkBus, rclkBus, ByPass, BusClk, BusClk, Vref, PwrUp, tclkpll, rclkpll);
rESDClk ECR(BusClk);
rPreLR PLR(hnl_179, hnl_180, hnl_181, hnl_182, hnl_183, hnl_184, hnl_185, hnl_186, hnl_187, hnl_188, hnl_189, hnl_190, hnl_191, hnl_192, hnl_193, hnl_194, BCSel_3_, BCSel_2_, BCSel_1_, BCSel_0_,
BDSel_3_, BDSel_2_, BDSel_1_, BDSel_0_, RCSel_3_, RCSel_2_, RCSel_1_, RCSel_0_, REnSel_3_, REnSel_2_, REnSel_1_, REnSel_0_, bist);
rLdREn LR(ldBC, ldBD, ldBE, rEn, rEnC, hnl_178, hnl_179, hnl_180, hnl_181, hnl_182, hnl_183, hnl_184, hnl_185, hnl_186, BESel_3_, BESel_2_, BESel_1_, BESel_0_, hnl_187, hnl_188, hnl_189, hnl_190,
hnl_191, hnl_192, hnl_193, hnl_194, ldEn, samplse, samplse_, sclk, se, si);
rClks K(SCANM_, SynClk, SynClkFd, Synint, pd, pd2, rclk, rclkpll, samplse, samplse_, sclk, se, slowClk_, tclk, tclkpll, ByPSel, ByPass, PhStall, PwrUp, Reset, SCANClk, SCANEn, SCANMode, StopR, StopT,
SynClkIn, preSlowClk, rclkASIC, rclkBus, rclkDrv_, tclkASIC, tclkBus, tclkDrv_);
ppoint I85(rEnC);
ppoint I81(SCANM_);
ppoint I80(pd);
ppoint I74(rEn);
ppoint I77(ldBC);
ppoint I76(ldBE);
ppoint I75(ldBD);
endmodule

module rVref (Vref, VrefPad);
output Vref;
input VrefPad;
supply1 vddA;
supply0 gndR;
supply1 vddR;
tranif1 N66(VrefPad, gndR, gndR);
resistPS R83(hnl_195, Vref);
resistPS R82(hnl_195, Vref);
resistPS R78(VrefPad, Vref);
tranif0 P67(VrefPad, vddR, vddR);
endmodule

module rLoadEn (ReqEn, Transmit, ldEn, Reset, SCANMode_, SynClk, bist, iotest, se, si);
output ReqEn, Transmit, ldEn;
input Reset, SCANMode_, SynClk, bist, iotest, se, si;
supply1 vddA;
supply0 gndR;
supply1 vddR;
nor #(0) U121(hnl_196, hnl_109, bist);
nor #(0) U117(hnl_197, hnl_198, hnl_199);
nor #(0) U116(ldend, hnl_197, hnl_196);
vqmsr rd(hnl_200, hnl_72, SynClk, SynClkL_);
vqmx02 I59(ReqEn, b3, hnl_200, hnl_26, SCANMode_);
vqmsrs I115(hnl_198, b3, SynClkL_, SynClk, se, se_, si);
vqmsrs lden(ldEn, ldend, SynClkL_, SynClk, se, se_, hnl_198);
not #(0) U122(hnl_199, iotest);
not #(0) U114(hnl_72, b3);
not #(0) U11(hnl_109, Reset);
not #(0) U57(Transmit, b3);
not #(0) U24(b3, ldEn);
not #(0) U74(se_, se);
not #(0) U23(SynClkL_, SynClk);
not #(0) U61(hnl_26, SCANMode_);
endmodule

module vqmxlat (Q_, D, clk, clk_, se, se_, si);
output Q_;
input D, clk, clk_, se, se_, si;
supply1 vddA;
supply0 gndR;
supply1 vddR;
vqlatw U8(Q_, hnl_137);
vqcxfr U6(hnl_137, clk, clk_, sh);
vqcxfr U11(sh, se, se_, si);
vqcxfr U1(sh, se_, se, D);
endmodule

module vqmsrsz (Q_, D, clk, clk_, se, se_, si);
output Q_;
input D, clk, clk_, se, se_, si;
supply1 vddA;
supply0 gndR;
supply1 vddR;
vqcxfr U25(Q_, clk, clk_, hnl_62);
vqcxfr U28(hnl_6, se_, se, D);
vqcxfr U27(hnl_6, se, se_, si);
vqcxfr U26(hnl_201, clk_, clk, hnl_6);
vqlatw U23(hnl_62, hnl_201);
vqlatw U24(hnl_63, Q_);
endmodule

module vqmsrsy (Q, Q_, D, clk, clk_, se, se_, si);
output Q, Q_;
input D, clk, clk_, se, se_, si;
supply1 vddA;
supply0 gndR;
supply1 vddR;
not #(0) U34(hnl_65, hnl_5);
vqlatw U28(hnl_5, hnl_6);
vqlatw U29(Q, hnl_201);
vqlatw U32(Q_, hnl_202);
vqcxfr U26(hnl_201, clk, clk_, hnl_5);
vqcxfr U27(hnl_6, clk_, clk, sh);
vqcxfr U30(sh, se, se_, si);
vqcxfr U31(sh, se_, se, D);
vqcxfr U33(hnl_202, clk, clk_, hnl_65);
endmodule

module rIOCtlA (loadBC, loadBC_, loadL1, loadL1_, loadL2, loadL2_, rEnLC, rEnLC_, rEnLD, rEnLD_, so, ldBC, ldBD, rEn, rEnC, scanM_, sclkL, sclkL_, se, si, tclkL, tclkL_);
output loadBC, loadBC_, loadL1, loadL1_, loadL2, loadL2_, rEnLC, rEnLC_, rEnLD, rEnLD_, so;
input ldBC, ldBD, rEn, rEnC, scanM_, sclkL, sclkL_, se, si, tclkL, tclkL_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
ppoint I136(tclkd);
ppoint I135(tclkd_);
ppoint I134(xclk);
ppoint I133(xclk_);
nor #(0) U10(hnl_203, nldb1_, se);
nor #(0) U109(hnl_204, nlbb_, se);
nor #(0) U16(hnl_37, nldb2_, se);
nand #(0) U20(hnl_35, nldb1, hnl_205);
nand #(0) U22(hnl_206, nldb2, hnl_205);
nand #(0) U115(hnl_207, nlbb, hnl_205);
vqmxlat I99(ndr1, nrd, sclkL_, sclkL, hnl_208, scanM_, vddR);
vqmxlat I97(nrd1_, nrd_, sclkL_, sclkL, hnl_208, scanM_, gndR);
vqmxlat I100(nrd2, hnl_209, sclkL_, sclkL, hnl_208, scanM_, vddR);
vqmxlat I98(nrd2_, hnl_210, sclkL_, sclkL, hnl_208, scanM_, gndR);
vqmx02 I124(tclkd, vddR, gndR, tclkL_, tclkL);
vqmx02 I121(tclkd_, vddR, gndR, tclkL, tclkL_);
vqmx02 I91(xclk_, vddR, gndR, vddR, gndR);
vqmx02 I92(xclk, vddR, gndR, vddR, gndR);
vqmsrsz I117(nlbb, nlba, tclkL_, tclkL, se, hnl_205, hnl_211);
vqmsrsz I9(nldb1_, nlda1_, tclkL_, tclkL, se, hnl_205, si);
vqmsrsz I25(nldb2, nlda2, tclkL_, tclkL, se, hnl_205, hnl_212);
vqmsrsz I110(nlbb_, nlba_, tclkL_, tclkL, se, hnl_205, hnl_94);
vqmsrsz I19(nldb1, nlda1, tclkL_, tclkL, se, hnl_205, hnl_213);
vqmsrsz I14(nldb2_, nlda2_, tclkL_, tclkL, se, hnl_205, hnl_19);
vqmsrsy I137(hnl_209, hnl_210, rEnC, sclkL, sclkL_, se, hnl_205, nrd);
vqmsrsy I65(nrd, nrd_, rEn, sclkL, sclkL_, se, hnl_205, nlb);
vqmsrsy I119(nlb, nlb_, ldBC, sclkL, sclkL_, se, hnl_205, nld);
vqmsrsy I1(nld, nld_, ldBD, sclkL, sclkL_, se, hnl_205, hnl_214);
vqlatch I95(nlda1, nld, tclkd_, tclkd);
vqlatch I112(nlba_, nlb_, tclkd_, tclkd);
vqlatch I94(nlda2_, nld_, tclkd_, tclkd);
vqlatch I113(nlba, nlb, tclkd_, tclkd);
vqlatch I96(nlda2, nld, tclkd_, tclkd);
vqlatch I93(nlda1_, nld_, tclkd_, tclkd);
not #(0) U140(hnl_214, hnl_215);
not #(0) U139(hnl_215, hnl_72);
not #(0) U75(rEnLD, ndr1);
not #(0) U87(rEnLD_, nrd1_);
not #(0) U11(loadL1_, hnl_203);
not #(0) U21(loadL1, hnl_35);
not #(0) U81(rEnLC, nrd2);
not #(0) U74(rEnLC_, nrd2_);
not #(0) U89(so, hnl_14);
not #(0) U70(hnl_208, scanM_);
not #(0) U88(hnl_14, hnl_209);
not #(0) U116(loadBC, hnl_207);
not #(0) U107(loadBC_, hnl_204);
not #(0) U24(loadL2, hnl_206);
not #(0) U12(loadL2_, hnl_37);
not #(0) U108(hnl_211, nlbb_);
not #(0) U54(hnl_212, nldb1);
not #(0) U55(hnl_213, nldb2_);
not #(0) U114(hnl_72, nlbb);
not #(0) U56(hnl_19, nldb1_);
not #(0) U42(hnl_94, nldb2);
not #(0) U32(hnl_205, se);
endmodule

module rCtrlL (ReqEn, Transmit, Vref, ldEn, loadBC, loadBC_, loadL1, loadL1_, loadL2, loadL2_, rEnLC, rEnLC_, rEnLD, rEnLD_, so_, Reset, SCANMode_, SynClk, VrefPad, bist, iotest, ldBC, ldBD, rEn,
rEnC, sclk, se, si_, tclk);
output ReqEn, Transmit, Vref, ldEn, loadBC, loadBC_, loadL1, loadL1_, loadL2, loadL2_, rEnLC, rEnLC_, rEnLD, rEnLD_, so_;
input Reset, SCANMode_, SynClk, VrefPad, bist, iotest, ldBC, ldBD, rEn, rEnC, sclk, se, si_, tclk;
supply1 vddA;
supply0 gndR;
supply1 vddR;
capN C1(vddR, gndR);
rVref SIO(Vref, VrefPad);
rLoadEn LE(ReqEn, Transmit, ldEn, Reset, SCANMode_, SynClk, bist, iotest, se, hnl_216);
rzerboB UBZT(tclkL, tclkL_, tclk);
rzerboB UBZS(sclkL, sclkL_, sclk);
rIOCtlA IOCA(loadBC, loadBC_, loadL1, loadL1_, loadL2, loadL2_, rEnLC, rEnLC_, rEnLD, rEnLD_, hnl_216, ldBC, ldBD, rEn, rEnC, SCANMode_, sclkL, sclkL_, se, hnl_41, tclkL, tclkL_);
ppoint I71(sclkL);
ppoint I72(sclkL_);
ppoint I70(tclkL_);
ppoint I69(tclkL);
not #(0) U68(so_, Transmit);
not #(0) U67(hnl_41, si_);
endmodule

module rIShift (even, odd, rd_7_, rd_6_, rd_5_, rd_4_, rd_3_, rd_2_, rd_1_, rd_0_, soE, soO, rEnL, rEnL_, rclkL, rclkL_, rdE, rdO_, scanM_, se, siE, siO);
output even, odd, rd_7_, rd_6_, rd_5_, rd_4_, rd_3_, rd_2_, rd_1_, rd_0_, soE, soO;
input rEnL, rEnL_, rclkL, rclkL_, rdE, rdO_, scanM_, se, siE, siO;
supply1 vddA;
supply0 gndR;
supply1 vddR;
vqmsrs E1(even, rdE, rclkL, rclkL_, se, hnl_217, siE);
vqmxfr I493(odd, siO, hnl_218, hnl_219, scanM_);
vqmsr O4(soO, r3, rclkL, rclkL_);
vqmsr E4(soE, r2, rclkL, rclkL_);
vqmsr O2(r5, odd, rclkL, rclkL_);
vqmsr O3(r3, r5, rclkL, rclkL_);
vqmsr E3(r2, r4, rclkL, rclkL_);
vqmsr E2(r4, even, rclkL, rclkL_);
vqlatch O1(hnl_218, rdO_, rclkL, rclkL_);
vqlatch R7(hnl_220, odd, rEnL, rEnL_);
vqlatch R6(hnl_221, even, rEnL, rEnL_);
vqlatch R5(hnl_222, r5, rEnL, rEnL_);
vqlatch R4(hnl_223, r4, rEnL, rEnL_);
vqlatch R3(hnl_224, r3, rEnL, rEnL_);
vqlatch R2(hnl_225, r2, rEnL, rEnL_);
vqlatch R1(hnl_226, soO, rEnL, rEnL_);
vqlatch R0(hnl_227, soE, rEnL, rEnL_);
not #(0) U266(hnl_217, se);
not #(0) U497(hnl_219, scanM_);
not #(0) U400(rd_0_, hnl_227);
not #(0) U399(rd_1_, hnl_226);
not #(0) U398(rd_2_, hnl_225);
not #(0) U397(rd_3_, hnl_224);
not #(0) U396(rd_4_, hnl_223);
not #(0) U395(rd_5_, hnl_222);
not #(0) U394(rd_6_, hnl_221);
not #(0) U267(rd_7_, hnl_220);
endmodule

module rOpad (pad, op_5_, op_4_, op_3_, op_2_, op_1_, op_0_);
output pad;
input op_5_, op_4_, op_3_, op_2_, op_1_, op_0_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
tranif1 N35(pad, gndR, gndR);
tranif1 N33(pad, gndR, op_5_);
tranif1 N29(pad, gndR, op_4_);
tranif1 N21(pad, gndR, op_3_);
tranif1 N19(pad, gndR, op_2_);
tranif1 N32(pad, gndR, op_1_);
tranif1 N20(pad, gndR, op_0_);
tranif0 P34(pad, vddR, vddR);
endmodule

module rOmux (op_5_, op_4_, op_3_, op_2_, op_1_, op_0_, evenData, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, oddData, tclkL, tclkL_b);
output op_5_, op_4_, op_3_, op_2_, op_1_, op_0_;
input evenData, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, oddData, tclkL, tclkL_b;
supply1 vddA;
supply0 gndR;
supply1 vddR;
not #(0) U115(op_5_, i5);
not #(0) U113(op_4_, i4);
not #(0) U112(op_3_, i3);
not #(0) U111(op_2_, i2);
not #(0) U82(op_1_, i1);
not #(0) U114(op_0_, i0);
nand #(1) U118(hnl_228, oddData, ictrl_2_);
nand #(1) U117(hnl_197, evenData, ictrl_2_);
nand #(1) U116(hnl_27, oddData, ictrl_1_);
nand #(1) U60(hnl_25, evenData, ictrl_1_);
nand #(1) U126(hnl_229, oddData, ictrl_0_);
nand #(1) U125(hnl_230, evenData, ictrl_0_);
nand #(1) U120(hnl_42, evenData, ictrl_3_);
nand #(1) U119(hnl_231, oddData, ictrl_3_);
nand #(1) U122(hnl_199, evenData, ictrl_4_);
nand #(1) U121(hnl_196, oddData, ictrl_4_);
nand #(1) U124(hnl_232, evenData, ictrl_5_);
nand #(1) U123(hnl_233, oddData, ictrl_5_);
vqcxfr U52(i5, tclkL, tclkL_b, hnl_233);
vqcxfr U99(i5, tclkL_b, tclkL, hnl_232);
vqcxfr U81(i1, tclkL, tclkL_b, hnl_27);
vqcxfr U62(i1, tclkL_b, tclkL, hnl_25);
vqcxfr U76(i0, tclkL, tclkL_b, hnl_229);
vqcxfr U66(i0, tclkL_b, tclkL, hnl_230);
vqcxfr U87(i2, tclkL_b, tclkL, hnl_197);
vqcxfr U75(i2, tclkL, tclkL_b, hnl_228);
vqcxfr U79(i3, tclkL_b, tclkL, hnl_42);
vqcxfr U53(i3, tclkL, tclkL_b, hnl_231);
vqcxfr U71(i4, tclkL_b, tclkL, hnl_199);
vqcxfr U56(i4, tclkL, tclkL_b, hnl_196);
endmodule

module rIObuf (rdE, rdO_, pad, Vref, evenData, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, oddData, pd, rclkL, rclkL_, scanM_, tclkL, tclkL_);
output rdE, rdO_;
inout pad;
input Vref, evenData, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, oddData, pd, rclkL, rclkL_, scanM_, tclkL, tclkL_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
vqlatch O0(rdO_, hnl_234, rclkL_, rclkL);
vqlatch E0(rdE, hnl_215, rclkL, rclkL_);
rOpad OP(pad, op_5_, op_4_, op_3_, op_2_, op_1_, op_0_);
rISamp ISE(hnl_235, hnl_236, pad, rclkL_, vbias, Vref);
rISamp ISO(hnl_237, hnl_238, pad, rclkL, vbias, Vref);
rISBiGn I136(vbias, pd);
rOmux OM(op_5_, op_4_, op_3_, op_2_, op_1_, op_0_, evenData, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, oddData, tclkL, tclkL_);
nand #(1) U141(hnl_234, hnl_238, scanM_);
nand #(1) U139(hnl_215, hnl_235, scanM_);
endmodule

module rOsftX (soE_, soO_, tdE, tdO, clk, clk_, dE, dO, scanM_, se, se_, siE, siO);
output soE_, soO_, tdE, tdO;
input clk, clk_, dE, dO, scanM_, se, se_, siE, siO;
supply1 vddA;
supply0 gndR;
supply1 vddR;
vqmxlat I4(tdE, dE, clk_, clk, se, se_, siE);
vqmxlat I11(hnl_239, dO, clk_, clk, se, se_, siO);
vqlatch I1(tdO, hnl_240, clk, clk_);
vqlatch I12(soE_, hnl_112, clk, clk_);
not #(0) U13(hnl_108, scanM_);
not #(0) U3(hnl_112, hnl_241);
not #(0) U2(hnl_240, hnl_239);
vqcxfr U7(soO_, hnl_108, scanM_, tdO);
vqcxfr U9(hnl_241, hnl_108, scanM_, tdE);
tranif1 N14(soO_, gndR, scanM_);
tranif1 N15(hnl_241, gndR, scanM_);
endmodule

module rOShift (soE_, tdE, tdO, Btd_7_, Btd_6_, Btd_5_, Btd_4_, Btd_3_, Btd_2_, Btd_1_, Btd_0_, bist, loadL, loadL_, scanM_, se, siO_, tclkL, tclkL_, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_,
td_0_);
output soE_, tdE, tdO;
input Btd_7_, Btd_6_, Btd_5_, Btd_4_, Btd_3_, Btd_2_, Btd_1_, Btd_0_, bist, loadL, loadL_, scanM_, se, siO_, tclkL, tclkL_, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_, td_0_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
not #(0) U111(hnl_242, bist);
rOsftX I131(soE_, hnl_243, tdE, tdO, tclkL_, tclkL, s0, s1, scanM_, loadL_, loadL, hnl_244, hnl_245);
nand #(0) U70(hnl_208, se, siO_);
nand #(0) U69(hnl_17, se, hnl_243);
vqmx02 T6(s6, Btd_6_, td_6_, bist, hnl_242);
vqmx02 T4(s4, Btd_4_, td_4_, bist, hnl_242);
vqmx02 T2(s2, Btd_2_, td_2_, bist, hnl_242);
vqmx02 T1(s1, Btd_1_, td_1_, bist, hnl_242);
vqmx02 T3(s3, Btd_3_, td_3_, bist, hnl_242);
vqmx02 T5(s5, Btd_5_, td_5_, bist, hnl_242);
vqmx02 T7(s7, Btd_7_, td_7_, bist, hnl_242);
vqmx02 T0(s0, Btd_0_, td_0_, bist, hnl_242);
vqmsrs O2(hnl_245, s3, tclkL_, tclkL, loadL_, loadL, hnl_246);
vqmsrs E2(hnl_244, s2, tclkL_, tclkL, loadL_, loadL, hnl_247);
vqmsrs E4(hnl_248, s6, tclkL_, tclkL, loadL_, loadL, hnl_17);
vqmsrs E3(hnl_247, s4, tclkL_, tclkL, loadL_, loadL, hnl_248);
vqmsrs O3(hnl_246, s5, tclkL_, tclkL, loadL_, loadL, hnl_249);
vqmsrs O4(hnl_249, s7, tclkL_, tclkL, loadL_, loadL, hnl_208);
endmodule

module rIOcell (rd_7_, rd_6_, rd_5_, rd_4_, rd_3_, rd_2_, rd_1_, rd_0_, soIE, soIO, soOE_, pad, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadL, loadL_, pd, rEnL, rEnL_,
rclk, scanM_, se, siIE, siIO, siOO_, srd_1_, srd_0_, tclk, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_, td_0_);
output rd_7_, rd_6_, rd_5_, rd_4_, rd_3_, rd_2_, rd_1_, rd_0_, soIE, soIO, soOE_;
inout pad;
input Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadL, loadL_, pd, rEnL, rEnL_, rclk, scanM_, se, siIE, siIO, siOO_, srd_1_, srd_0_, tclk, td_7_, td_6_, td_5_, td_4_,
td_3_, td_2_, td_1_, td_0_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
rIShift IS(hnl_250, hnl_251, rd_7_, rd_6_, rd_5_, rd_4_, rd_3_, rd_2_, rd_1_, rd_0_, soIE, soIO, rEnL, rEnL_, rclkL, rclkL_, rdE, rdO_, scanM_, se, siIE, siIO);
rIObuf IOB(rdE, rdO_, pad, Vref, tdE, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, tdO, pd, rclkL, rclkL_, scanM_, tclkL, tclkL_);
rOShift OS(soOE_, tdE, tdO, srd_1_, srd_0_, rd_7_, rd_6_, rd_5_, rd_4_, rd_3_, rd_2_, bist, loadL, loadL_, scanM_, se, siOO_, tclkL, tclkL_, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_, td_0_);
rzerboB UZBT(tclkL, tclkL_, tclk);
rzerboB UZBR(rclkL, rclkL_, rclk);
ppoint I88(rdO_);
ppoint I89(rdE);
ppoint I90(hnl_250);
ppoint I91(hnl_251);
ppoint I92(rclkL);
ppoint I93(rclkL_);
ppoint I94(tclkL);
ppoint I95(tclkL_);
ppoint I96(tdO);
ppoint I97(tdE);
endmodule

module rRACL (ReqEn, Transmit, Vref, brfoo_7_, brfoo_6_, brfoo_5_, brfoo_4_, brfoo_3_, brfoo_2_, brfoo_1_, brfoo_0_, ldEn, rfoo_39_, rfoo_38_, rfoo_37_, rfoo_36_, rfoo_35_, rfoo_34_, rfoo_33_,
rfoo_32_, rfoo_31_, rfoo_30_, rfoo_29_, rfoo_28_, rfoo_27_, rfoo_26_, rfoo_25_, rfoo_24_, rfoo_23_, rfoo_22_, rfoo_21_, rfoo_20_, rfoo_19_, rfoo_18_, rfoo_17_, rfoo_16_, rfoo_15_, rfoo_14_, rfoo_13_,
rfoo_12_, rfoo_11_, rfoo_10_, rfoo_9_, rfoo_8_, rfoo_7_, rfoo_6_, rfoo_5_, rfoo_4_, rfoo_3_, rfoo_2_, rfoo_1_, rfoo_0_, so_, BusCtrl, BusData_4_, BusData_3_, BusData_2_, BusData_1_, BusData_0_,
Reset, SynClk, VrefPad, bist, btfoo_7_, btfoo_6_, btfoo_5_, btfoo_4_, btfoo_3_, btfoo_2_, btfoo_1_, btfoo_0_, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, iotest, ldBC, ldBD, pd, pd2,
rEn, rEnC, rclk, scanM_, sclk, se, si, srd_1_, srd_0_, tclk, tfoo_39_, tfoo_38_, tfoo_37_, tfoo_36_, tfoo_35_, tfoo_34_, tfoo_33_, tfoo_32_, tfoo_31_, tfoo_30_, tfoo_29_, tfoo_28_, tfoo_27_,
tfoo_26_, tfoo_25_, tfoo_24_, tfoo_23_, tfoo_22_, tfoo_21_, tfoo_20_, tfoo_19_, tfoo_18_, tfoo_17_, tfoo_16_, tfoo_15_, tfoo_14_, tfoo_13_, tfoo_12_, tfoo_11_, tfoo_10_, tfoo_9_, tfoo_8_, tfoo_7_,
tfoo_6_, tfoo_5_, tfoo_4_, tfoo_3_, tfoo_2_, tfoo_1_, tfoo_0_);
output ReqEn, Transmit, Vref, brfoo_7_, brfoo_6_, brfoo_5_, brfoo_4_, brfoo_3_, brfoo_2_, brfoo_1_, brfoo_0_, ldEn, rfoo_39_, rfoo_38_, rfoo_37_, rfoo_36_, rfoo_35_, rfoo_34_, rfoo_33_, rfoo_32_,
rfoo_31_, rfoo_30_, rfoo_29_, rfoo_28_, rfoo_27_, rfoo_26_, rfoo_25_, rfoo_24_, rfoo_23_, rfoo_22_, rfoo_21_, rfoo_20_, rfoo_19_, rfoo_18_, rfoo_17_, rfoo_16_, rfoo_15_, rfoo_14_, rfoo_13_, rfoo_12_,
rfoo_11_, rfoo_10_, rfoo_9_, rfoo_8_, rfoo_7_, rfoo_6_, rfoo_5_, rfoo_4_, rfoo_3_, rfoo_2_, rfoo_1_, rfoo_0_, so_;
inout BusCtrl, BusData_4_, BusData_3_, BusData_2_, BusData_1_, BusData_0_;
input Reset, SynClk, VrefPad, bist, btfoo_7_, btfoo_6_, btfoo_5_, btfoo_4_, btfoo_3_, btfoo_2_, btfoo_1_, btfoo_0_, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, iotest, ldBC, ldBD, pd,
pd2, rEn, rEnC, rclk, scanM_, sclk, se, si, srd_1_, srd_0_, tclk, tfoo_39_, tfoo_38_, tfoo_37_, tfoo_36_, tfoo_35_, tfoo_34_, tfoo_33_, tfoo_32_, tfoo_31_, tfoo_30_, tfoo_29_, tfoo_28_, tfoo_27_,
tfoo_26_, tfoo_25_, tfoo_24_, tfoo_23_, tfoo_22_, tfoo_21_, tfoo_20_, tfoo_19_, tfoo_18_, tfoo_17_, tfoo_16_, tfoo_15_, tfoo_14_, tfoo_13_, tfoo_12_, tfoo_11_, tfoo_10_, tfoo_9_, tfoo_8_, tfoo_7_,
tfoo_6_, tfoo_5_, tfoo_4_, tfoo_3_, tfoo_2_, tfoo_1_, tfoo_0_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
rCtrlL CL(ReqEn, Transmit, Vref, ldEn, loadBC, loadBC_, loadA1, loadA1_, loadA2, loadA2_, rEnA2, rEnA2_, rEnA1, rEnA1_, hnl_252, Reset, scanM_, SynClk, VrefPad, bist, iotest, ldBC, ldBD, rEn, rEnC,
sclk, se, hnl_253, tclk);
rIOcell IO_3_(rfoo_31_, rfoo_30_, rfoo_29_, rfoo_28_, rfoo_27_, rfoo_26_, rfoo_25_, rfoo_24_, net4330, net4331, net4320, BusData_3_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_,
ictrl_0_, loadA1, loadA1_, pd, rEnA1, rEnA1_, rclk, scanM_, se, hnl_254, hnl_255, hnl_252, net4324_0_, net4324_1_, tclk, tfoo_31_, tfoo_30_, tfoo_29_, tfoo_28_, tfoo_27_, tfoo_26_, tfoo_25_,
tfoo_24_);
rIOcell IO_0_(rfoo_7_, rfoo_6_, rfoo_5_, rfoo_4_, rfoo_3_, rfoo_2_, rfoo_1_, rfoo_0_, net4325, net4323, so_, BusData_0_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_,
loadA1, loadA1_, pd, rEnA1, rEnA1_, rclk, scanM_, se, net4326, net4327, net4322, rfoo_9_, rfoo_8_, tclk, tfoo_7_, tfoo_6_, tfoo_5_, tfoo_4_, tfoo_3_, tfoo_2_, tfoo_1_, tfoo_0_);
rIOcell BC(brfoo_7_, brfoo_6_, brfoo_5_, brfoo_4_, brfoo_3_, brfoo_2_, brfoo_1_, brfoo_0_, hnl_256, hnl_257, hnl_253, BusCtrl, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_,
loadBC, loadBC_, pd2, rEnA2, rEnA2_, sclk, scanM_, se, net4332, net4333, net4321, rfoo_33_, rfoo_32_, tclk, btfoo_7_, btfoo_6_, btfoo_5_, btfoo_4_, btfoo_3_, btfoo_2_, btfoo_1_, btfoo_0_);
rIOcell IO_2_(rfoo_23_, rfoo_22_, rfoo_21_, rfoo_20_, rfoo_19_, rfoo_18_, rfoo_17_, rfoo_16_, net4328, net4329, net4319, BusData_2_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_,
ictrl_0_, loadA1, loadA1_, pd, rEnA1, rEnA1_, rclk, scanM_, se, net4330, net4331, net4320, rfoo_25_, rfoo_24_, tclk, tfoo_23_, tfoo_22_, tfoo_21_, tfoo_20_, tfoo_19_, tfoo_18_, tfoo_17_, tfoo_16_);
rIOcell IO_1_(rfoo_15_, rfoo_14_, rfoo_13_, rfoo_12_, rfoo_11_, rfoo_10_, rfoo_9_, rfoo_8_, net4326, net4327, net4322, BusData_1_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_,
ictrl_0_, loadA1, loadA1_, pd, rEnA1, rEnA1_, rclk, scanM_, se, net4328, net4329, net4319, rfoo_17_, rfoo_16_, tclk, tfoo_15_, tfoo_14_, tfoo_13_, tfoo_12_, tfoo_11_, tfoo_10_, tfoo_9_, tfoo_8_);
rIOcell IO_4_(rfoo_39_, rfoo_38_, rfoo_37_, rfoo_36_, rfoo_35_, rfoo_34_, rfoo_33_, rfoo_32_, net4332, net4333, net4321, BusData_4_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_,
ictrl_0_, loadA2, loadA2_, pd, rEnA1, rEnA1_, rclk, scanM_, se, hnl_258, si, hnl_11, srd_1_, srd_0_, tclk, tfoo_39_, tfoo_38_, tfoo_37_, tfoo_36_, tfoo_35_, tfoo_34_, tfoo_33_, tfoo_32_);
ppoint I90(rEnA2_);
ppoint I89(rEnA2);
ppoint I88(loadBC_);
ppoint I87(loadBC);
ppoint I86(rEnA1_);
ppoint I85(rEnA1);
ppoint I84(loadA2_);
ppoint I83(loadA2);
ppoint I82(loadA1_);
ppoint I81(loadA1);
ppoint I80(rEnA1_);
ppoint I79(rEnA1);
not #(0) U78(hnl_255, hnl_259);
not #(0) U77(hnl_259, hnl_257);
not #(0) U76(hnl_254, hnl_260);
not #(0) U75(hnl_260, hnl_256);
not #(0) U69_0_(net4324_0_, net4318_0_);
not #(0) U69_1_(net4324_1_, net4318_1_);
not #(0) U68_0_(net4318_0_, brfoo_1_);
not #(0) U68_1_(net4318_1_, brfoo_0_);
not #(0) U66(hnl_32, net4323);
not #(0) U65(hnl_258, hnl_32);
not #(0) U63(hnl_11, net4325);
endmodule

module rUDcell (cOut, ictrl, so, tDrv_, Din, carryIn, ictrlEn, ictrlLd, ictrlOn, se, se_, si, slowClk, slowClk_, up);
output cOut, ictrl, so, tDrv_;
input Din, carryIn, ictrlEn, ictrlLd, ictrlOn, se, se_, si, slowClk, slowClk_, up;
supply1 vddA;
supply0 gndR;
supply1 vddR;
vqmsrs I1(so, hnl_261, slowClk_, slowClk, se, se_, si);
vqlatch I2(ictrl, so, ictrlLd, hnl_63);
nand #(0) U21(hnl_106, hnl_262, carryIn);
nand #(0) U26(tDrv_, hnl_36, ictrlOn);
vqmx02 I3(hnl_261, Din, hnl_263, hnl_60, ictrlEn);
vqmx02 I5(hnl_262, hnl_36, so, hnl_35, up);
vqmx02 I4(hnl_263, hnl_36, so, carryIn, hnl_37);
not #(0) U24(hnl_63, ictrlLd);
not #(0) U15(hnl_60, ictrlEn);
not #(0) U16(hnl_37, carryIn);
not #(0) U20(hnl_35, up);
not #(0) U22(cOut, hnl_106);
not #(0) U18(hnl_36, so);
endmodule

module rUDCntr (ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, op_5_, op_4_, op_3_, op_2_, op_1_, op_0_, so, Din_5_, Din_4_, Din_3_, Din_2_, Din_1_, Din_0_, IctrlEn, IctrlLd, carryIn,
ictrlOn, scanM_, se, si, slowClk, slowClk_, up);
output ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, op_5_, op_4_, op_3_, op_2_, op_1_, op_0_, so;
input Din_5_, Din_4_, Din_3_, Din_2_, Din_1_, Din_0_, IctrlEn, IctrlLd, carryIn, ictrlOn, scanM_, se, si, slowClk, slowClk_, up;
supply1 vddA;
supply0 gndR;
supply1 vddR;
rUDcell Q5(hnl_264, hnl_265, hnl_266, hnl_267, Din_5_, hnl_268, IctrlEn, IctrlLd, ictrlOn, se, se_, hnl_269, slowClk, slowClk_, up);
rUDcell Q4(hnl_268, hnl_270, hnl_269, hnl_271, Din_4_, hnl_272, IctrlEn, IctrlLd, ictrlOn, se, se_, hnl_273, slowClk, slowClk_, up);
rUDcell Q3(hnl_272, hnl_274, hnl_273, hnl_275, Din_3_, hnl_276, IctrlEn, IctrlLd, ictrlOn, se, se_, hnl_277, slowClk, slowClk_, up);
rUDcell Q2(hnl_276, hnl_278, hnl_277, hnl_279, Din_2_, hnl_280, IctrlEn, IctrlLd, ictrlOn, se, se_, hnl_281, slowClk, slowClk_, up);
rUDcell Q1(hnl_280, hnl_282, hnl_281, hnl_283, Din_1_, hnl_284, IctrlEn, IctrlLd, ictrlOn, se, se_, hnl_285, slowClk, slowClk_, up);
rUDcell Q0(hnl_284, hnl_286, hnl_285, hnl_287, Din_0_, icarryin, IctrlEn, IctrlLd, ictrlOn, se, se_, si, slowClk, slowClk_, up);
vqao21 U54(icarryin, scanM_, hnl_288, hnl_289);
vqmsr I49(hnl_288, hnl_264, hnl_158, ictrlOn);
not #(0) U39(op_5_, hnl_267);
not #(0) U38(op_4_, hnl_271);
not #(0) U37(op_3_, hnl_275);
not #(0) U35(op_1_, hnl_283);
not #(0) U36(op_2_, hnl_279);
not #(0) U34(op_0_, hnl_287);
not #(0) U42(se_, se);
not #(0) U46(hnl_290, hnl_266);
not #(0) U50(so, hnl_290);
not #(0) U51(hnl_289, carryIn);
not #(0) U24(hnl_63, hnl_270);
not #(0) U27(hnl_64, hnl_274);
not #(0) U28(ictrl_2_, hnl_291);
not #(0) U29(hnl_291, hnl_278);
not #(0) U30(hnl_292, hnl_282);
not #(0) U32(hnl_205, hnl_286);
not #(0) U53(hnl_158, ictrlOn);
not #(0) U22(hnl_206, hnl_265);
not #(0) U23(ictrl_5_, gndR);
not #(0) U25(ictrl_4_, vddR);
not #(0) U26(ictrl_3_, gndR);
not #(0) U31(ictrl_1_, vddR);
not #(0) U33(ictrl_0_, gndR);
endmodule

module rCCFsm (add, carryIn, so, sub, ictrlOn, reset, se, si, slowClk, slowClk_, up);
output add, carryIn, so, sub;
input ictrlOn, reset, se, si, slowClk, slowClk_, up;
supply1 vddA;
supply0 gndR;
supply1 vddR;
vqmsrs S1(o1, i1, slowClk_, slowClk, se, hnl_39, o0);
vqmsrs S0(o0, i0, slowClk_, slowClk, se, hnl_39, si);
nand #(0) U6(hnl_293, up, hnl_93, hnl_110);
nand #(0) U5(hnl_111, hnl_110, hnl_93, hnl_109);
nor #(0) U9(hnl_110, o1, o0);
nand #(0) U17(hnl_107, o0, ictrlOn);
nand #(0) U20(hnl_35, o1, ictrlOn);
nand #(0) U4(hnl_9, hnl_109, o0);
nand #(0) U3(hnl_112, up, o1);
nand #(0) U13(carryIn, hnl_112, hnl_9);
not #(0) U7(i1, hnl_293);
not #(0) U8(i0, hnl_111);
not #(0) U11(hnl_109, up);
not #(0) U33(hnl_39, se);
not #(0) U36(hnl_93, reset);
not #(0) U16(sub, hnl_107);
not #(0) U19(add, hnl_35);
not #(0) U28(hnl_5, o1);
not #(0) U29(so, hnl_5);
endmodule

module rCCtrl (ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, so, CCtlEn, CCtlI_5_, CCtlI_4_, CCtlI_3_, CCtlI_2_, CCtlI_1_, CCtlI_0_, CCtlPgm, IctrlLd, Vref, ictrlOn, pd2, reset, scanM_,
se, si, slowClk_);
output ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, so;
input CCtlEn, CCtlI_5_, CCtlI_4_, CCtlI_3_, CCtlI_2_, CCtlI_1_, CCtlI_0_, CCtlPgm, IctrlLd, Vref, ictrlOn, pd2, reset, scanM_, se, si, slowClk_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
rCCBiGn BG(hnl_294, pd2);
rUDCntr C(ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, op_5_, op_4_, op_3_, op_2_, op_1_, op_0_, hnl_295, CCtlI_5_, CCtlI_4_, CCtlI_3_, CCtlI_2_, CCtlI_1_, CCtlI_0_, CCtlEn, IctrlLd,
hnl_296, ictrlOn, scanM_, se, si, slowClk, slowClk_, hnl_297);
rCCFsm F(hnl_298, hnl_296, so, hnl_299, ictrlOn, reset, se, hnl_295, slowClk, slowClk_, hnl_297);
rCCAnal A(hnl_297, op_5_, op_4_, op_3_, op_2_, op_1_, op_0_, hnl_299, hnl_298, CCtlPgm, hnl_294, Vref, ictrlOn, slowClk, scanM_);
not #(0) U54(slowClk, slowClk_);
endmodule

module rIOCtlB (loadBE, loadBE_, loadL1, loadL1_, loadL2, loadL2_, rEnL1, rEnL1_, rEnL2, rEnL2_, so, ExtBE, ldBD, ldBE, rEn, scanM_, sclkL, sclkL_, se, si, tclkL, tclkL_);
output loadBE, loadBE_, loadL1, loadL1_, loadL2, loadL2_, rEnL1, rEnL1_, rEnL2, rEnL2_, so;
input ExtBE, ldBD, ldBE, rEn, scanM_, sclkL, sclkL_, se, si, tclkL, tclkL_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
ppoint I127(xclk_);
ppoint I128(xclk);
ppoint I129(tclkd_);
ppoint I130(tclkd);
nor #(0) U35(hnl_95, nldb2_, se);
nor #(0) U107(hnl_300, nlbb_, se);
nor #(0) U47(hnl_301, nldb1_, se);
nor #(0) U109(loadBE_, hnl_300, ExtBE);
nand #(0) U27(hnl_64, nldb2, hnl_61);
nand #(0) U77(hnl_259, nldb1, hnl_61);
nand #(0) U116(hnl_27, nlbb, hnl_61);
nand #(0) U113(loadBE, hnl_27, hnl_42);
vqmxlat I95(nrd2, nrd, sclkL_, sclkL, hnl_92, scanM_, vddR);
vqmxlat I97(nrd2_, nrd_, sclkL_, sclkL, hnl_92, scanM_, gndR);
vqmxlat I96(nrd1, nrd, sclkL_, sclkL, hnl_92, scanM_, vddR);
vqmxlat I98(nrd1_, nrd_, sclkL_, sclkL, hnl_92, scanM_, gndR);
vqmx02 I88(xclk_, vddR, gndR, vddR, gndR);
vqmx02 I85(xclk, vddR, gndR, vddR, gndR);
vqmx02 I126(tclkd_, vddR, gndR, tclkL, tclkL_);
vqmx02 I124(tclkd, vddR, gndR, tclkL_, tclkL);
vqmsrsz I111(nlbb, nlba, tclkL_, tclkL, se, hnl_61, hnl_211);
vqmsrsz I105(nlbb_, nlba_, tclkL_, tclkL, se, hnl_61, hnl_100);
vqmsrsz I28(nldb1_, nlda1_, tclkL_, tclkL, se, hnl_61, si);
vqmsrsz I10(nldb2_, nlda2_, tclkL_, tclkL, se, hnl_61, hnl_38);
vqmsrsz I72(nldb1, nlda1, tclkL_, tclkL, se, hnl_61, hnl_2);
vqmsrsz I55(nldb2, nlda2, tclkL_, tclkL, se, hnl_61, hnl_37);
vqmsrsy I42(nld, nld_, ldBD, sclkL, sclkL_, se, hnl_61, hnl_77);
vqmsrsy I29(nrd, nrd_, rEn, sclkL, sclkL_, se, hnl_61, nlb);
vqmsrsy I117(nlb, nlb_, ldBE, sclkL, sclkL_, se, hnl_61, nld);
vqlatch I93(nlda1_, nld_, tclkd_, tclkd);
vqlatch I92(nlda2_, nld_, tclkd_, tclkd);
vqlatch I110(nlba_, nlb_, tclkd_, tclkd);
vqlatch I94(nlda1, nld, tclkd_, tclkd);
vqlatch I114(nlba, nlb, tclkd_, tclkd);
vqlatch I91(nlda2, nld, tclkd_, tclkd);
not #(0) U132(hnl_77, hnl_29);
not #(0) U131(hnl_29, hnl_207);
not #(0) U19(hnl_61, se);
not #(0) U16(hnl_37, nldb1);
not #(0) U9(hnl_110, nrd);
not #(0) U43(hnl_92, scanM_);
not #(0) U31(hnl_2, nldb2_);
not #(0) U115(hnl_207, nlbb);
not #(0) U26(hnl_38, nldb1_);
not #(0) U38(hnl_100, nldb2);
not #(0) U108(hnl_211, nlbb_);
not #(0) U3(loadL1, hnl_259);
not #(0) U75(rEnL1, nrd1);
not #(0) U23(rEnL1_, nrd1_);
not #(0) U58(loadL1_, hnl_301);
not #(0) U49(so, hnl_110);
not #(0) U120(hnl_42, ExtBE);
not #(0) U44(loadL2, hnl_64);
not #(0) U57(rEnL2_, nrd2_);
not #(0) U50(rEnL2, nrd2);
not #(0) U71(loadL2_, hnl_95);
endmodule

module rBEcell (pad, soOE_, ExtBE, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadL, loadL_, scanM_, se, siOO_, tclkL, tclkL_, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_,
td_0_);
output pad, soOE_;
input ExtBE, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadL, loadL_, scanM_, se, siOO_, tclkL, tclkL_, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_, td_0_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
rOShift OS(soOE_, tdE, tdO, gndR, gndR, gndR, gndR, gndR, gndR, vddR, vddR, ExtBE, loadL, loadL_, scanM_, se, siOO_, tclkL, tclkL_, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_, td_0_);
rOmux OM(op_5_, op_4_, op_3_, op_2_, op_1_, op_0_, tdE, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, tdO, tclkL, tclkL_);
rOpad OP(pad, op_5_, op_4_, op_3_, op_2_, op_1_, op_0_);
endmodule

module rCtrlR (loadL1, loadL1_, loadL2, loadL2_, pad, rEnL1, rEnL1_, rEnL2, rEnL2_, so, soOE_, ExtBE, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, ldBD, ldBE, rEn, scanM_, sclk, se,
si, siOO_, tclk, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_, td_0_);
output loadL1, loadL1_, loadL2, loadL2_, pad, rEnL1, rEnL1_, rEnL2, rEnL2_, so, soOE_;
input ExtBE, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, ldBD, ldBE, rEn, scanM_, sclk, se, si, siOO_, tclk, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_, td_0_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
not #(0) U62(hnl_40, hnl_26);
not #(0) U61(hnl_26, si);
rIOCtlB IOCB(loadBE, loadBE_, loadL1, loadL1_, loadL2, loadL2_, rEnL1, rEnL1_, rEnL2, rEnL2_, so, ExtBE, ldBD, ldBE, rEn, scanM_, sclkL, sclkL_, se, hnl_40, tclkL, tclkL_);
rBEcell BE(pad, soOE_, ExtBE, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadBE, loadBE_, scanM_, se, siOO_, tclkL, tclkL_, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_, td_0_);
rzerboB BZT(tclkL, tclkL_, tclk);
rzerboB BZS(sclkL, sclkL_, sclk);
ppoint I55(loadBE_);
ppoint I56(loadBE);
ppoint I57(tclkL);
ppoint I58(tclkL_);
ppoint I59(sclkL);
ppoint I60(sclkL_);
endmodule

module rRACR (BusEnable, rfoo_71_, rfoo_70_, rfoo_69_, rfoo_68_, rfoo_67_, rfoo_66_, rfoo_65_, rfoo_64_, rfoo_63_, rfoo_62_, rfoo_61_, rfoo_60_, rfoo_59_, rfoo_58_, rfoo_57_, rfoo_56_, rfoo_55_,
rfoo_54_, rfoo_53_, rfoo_52_, rfoo_51_, rfoo_50_, rfoo_49_, rfoo_48_, rfoo_47_, rfoo_46_, rfoo_45_, rfoo_44_, rfoo_43_, rfoo_42_, rfoo_41_, rfoo_40_, soIE5, soOE5, srdo_1_, srdo_0_, BusData_8_,
BusData_7_, BusData_6_, BusData_5_, ExtBE, Vref, bist, etfoo_7_, etfoo_6_, etfoo_5_, etfoo_4_, etfoo_3_, etfoo_2_, etfoo_1_, etfoo_0_, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_,
ldBD, ldBE, pd, rEn, rclk, scanM_, sclk, se, siIO8, siOO8, srd_1_, srd_0_, tclk, tfoo_71_, tfoo_70_, tfoo_69_, tfoo_68_, tfoo_67_, tfoo_66_, tfoo_65_, tfoo_64_, tfoo_63_, tfoo_62_, tfoo_61_,
tfoo_60_, tfoo_59_, tfoo_58_, tfoo_57_, tfoo_56_, tfoo_55_, tfoo_54_, tfoo_53_, tfoo_52_, tfoo_51_, tfoo_50_, tfoo_49_, tfoo_48_, tfoo_47_, tfoo_46_, tfoo_45_, tfoo_44_, tfoo_43_, tfoo_42_, tfoo_41_,
tfoo_40_);
output BusEnable, rfoo_71_, rfoo_70_, rfoo_69_, rfoo_68_, rfoo_67_, rfoo_66_, rfoo_65_, rfoo_64_, rfoo_63_, rfoo_62_, rfoo_61_, rfoo_60_, rfoo_59_, rfoo_58_, rfoo_57_, rfoo_56_, rfoo_55_, rfoo_54_,
rfoo_53_, rfoo_52_, rfoo_51_, rfoo_50_, rfoo_49_, rfoo_48_, rfoo_47_, rfoo_46_, rfoo_45_, rfoo_44_, rfoo_43_, rfoo_42_, rfoo_41_, rfoo_40_, soIE5, soOE5, srdo_1_, srdo_0_;
inout BusData_8_, BusData_7_, BusData_6_, BusData_5_;
input ExtBE, Vref, bist, etfoo_7_, etfoo_6_, etfoo_5_, etfoo_4_, etfoo_3_, etfoo_2_, etfoo_1_, etfoo_0_, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, ldBD, ldBE, pd, rEn, rclk, scanM_,
sclk, se, siIO8, siOO8, srd_1_, srd_0_, tclk, tfoo_71_, tfoo_70_, tfoo_69_, tfoo_68_, tfoo_67_, tfoo_66_, tfoo_65_, tfoo_64_, tfoo_63_, tfoo_62_, tfoo_61_, tfoo_60_, tfoo_59_, tfoo_58_, tfoo_57_,
tfoo_56_, tfoo_55_, tfoo_54_, tfoo_53_, tfoo_52_, tfoo_51_, tfoo_50_, tfoo_49_, tfoo_48_, tfoo_47_, tfoo_46_, tfoo_45_, tfoo_44_, tfoo_43_, tfoo_42_, tfoo_41_, tfoo_40_;
supply1 vddA;
supply0 gndR;
supply1 vddR;
nor #(0) U82(soIE5, hnl_24, scanM_);
rIOcell IO_8_(rfoo_71_, rfoo_70_, rfoo_69_, rfoo_68_, rfoo_67_, rfoo_66_, rfoo_65_, rfoo_64_, net3483, net3484, net3475, BusData_8_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_,
ictrl_0_, loadB1, loadB1_, pd, rEnB1, rEnB1_, rclk, scanM_, se, hnl_22, siIO8, hnl_33, srd_1_, srd_0_, tclk, tfoo_71_, tfoo_70_, tfoo_69_, tfoo_68_, tfoo_67_, tfoo_66_, tfoo_65_, tfoo_64_);
rIOcell IO_7_(rfoo_63_, rfoo_62_, rfoo_61_, rfoo_60_, rfoo_59_, rfoo_58_, rfoo_57_, rfoo_56_, net3482, net3474, net3473, BusData_7_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_,
ictrl_0_, loadB1, loadB1_, pd, rEnB1, rEnB1_, rclk, scanM_, se, net3483, net3484, net3475, rfoo_65_, rfoo_64_, tclk, tfoo_63_, tfoo_62_, tfoo_61_, tfoo_60_, tfoo_59_, tfoo_58_, tfoo_57_, tfoo_56_);
rIOcell IO_6_(rfoo_55_, rfoo_54_, rfoo_53_, rfoo_52_, rfoo_51_, rfoo_50_, rfoo_49_, rfoo_48_, net3480, net3481, net3472, BusData_6_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_,
ictrl_0_, loadB2, loadB2_, pd, rEnB2, rEnB2_, rclk, scanM_, se, hnl_44, hnl_302, hnl_303, net3478_0_, net3478_1_, tclk, tfoo_55_, tfoo_54_, tfoo_53_, tfoo_52_, tfoo_51_, tfoo_50_, tfoo_49_,
tfoo_48_);
rIOcell IO_5_(rfoo_47_, rfoo_46_, rfoo_45_, rfoo_44_, rfoo_43_, rfoo_42_, rfoo_41_, rfoo_40_, net3470, net3476, net3471, BusData_5_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_,
ictrl_0_, loadB2, loadB2_, pd, rEnB2, rEnB2_, rclk, scanM_, se, net3480, net3481, net3472, rfoo_49_, rfoo_48_, tclk, tfoo_47_, tfoo_46_, tfoo_45_, tfoo_44_, tfoo_43_, tfoo_42_, tfoo_41_, tfoo_40_);
rCtrlR CR(loadB1, loadB1_, loadB2, loadB2_, BusEnable, rEnB1, rEnB1_, rEnB2, rEnB2_, hnl_302, hnl_303, ExtBE, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, ldBD, ldBE, rEn, scanM_,
sclk, se, hnl_304, net3473, tclk, etfoo_7_, etfoo_6_, etfoo_5_, etfoo_4_, etfoo_3_, etfoo_2_, etfoo_1_, etfoo_0_);
ppoint I97(loadB2);
ppoint I98(loadB2_);
ppoint I99(rEnB2_);
ppoint I100(rEnB2);
ppoint I101(loadB1_);
ppoint I102(rEnB1);
ppoint I103(loadB1);
ppoint I104(rEnB1_);
not #(0) U106(hnl_305, hnl_306);
not #(0) U105(hnl_306, net3471);
not #(0) U75_0_(net3479_0_, rfoo_57_);
not #(0) U75_1_(net3479_1_, rfoo_56_);
not #(0) U76_0_(net3478_0_, net3479_0_);
not #(0) U76_1_(net3478_1_, net3479_1_);
not #(0) U77_0_(srdo_1_, net3477_0_);
not #(0) U77_1_(srdo_0_, net3477_1_);
not #(0) U78_0_(net3477_0_, rfoo_41_);
not #(0) U78_1_(net3477_1_, rfoo_40_);
not #(0) U80(hnl_22, hnl_16);
not #(0) U81(hnl_16, net3476);
not #(0) U83(hnl_24, net3470);
not #(0) U84(soOE5, hnl_305);
not #(0) U85(hnl_33, siOO8);
not #(0) U91(hnl_307, net3482);
not #(0) U92(hnl_44, hnl_307);
not #(0) U93(hnl_154, net3474);
not #(0) U94(hnl_304, hnl_154);
endmodule

module rac(RData7, RData6, RData5, RData4, RData3, RData2, RData1, RData0,
 SynClk, SynClkFd,
 BusEnable, BISTFlag, SCANOut,
 BusCtrl, BusData,
 BusClk, BDSel, BCSel, BESel, RDSel, RCSel,
 Reset,
 TData7, TData6, TData5, TData4, TData3, TData2, TData1, TData0,
 Vref, ASynIn, ASynOut, Transmit, 
 BISTMode, IOSTMode, SCANMode, SCANClk, SCANEn, SCANIn, SynClkIn,
 CCtlEn, CCtlLd, CCtlI, CCtlO, CCtlPgm, PwrUp, ExtBE, StopR, StopT,
 ByPass, ByPSel, rclkASIC, tclkASIC, PhStall);
 
output  [9:0]   RData7, RData6, RData5, RData4, RData3, RData2, RData1, RData0;
output          SynClk, SynClkFd;
output          BusEnable;
output          BISTFlag, SCANOut;
output  [5:0]   CCtlO;
output          ASynIn, ASynOut, Transmit;
 
inout           BusCtrl;
inout   [8:0]   BusData;
input           BusClk;
input   [3:0]   BDSel, BCSel, BESel, RDSel, RCSel;
input           Reset;
input   [10:0]  TData7, TData6, TData5, TData4, TData3, TData2, TData1, TData0;
input           Vref;
input           BISTMode, IOSTMode, SCANMode, SCANClk, SCANEn, SCANIn, SynClkIn;
input           CCtlEn, CCtlLd;
input   [5:0]   CCtlI;
input           CCtlPgm, PwrUp, ExtBE, StopR, StopT;
input           ByPass, ByPSel, rclkASIC, tclkASIC, PhStall;
 
wire          ReqEn;
wire          ASynIn, ASynOut, Transmit;
wire  [5:0]   CCtlO;

supply1 vddA;
supply0 gndR;
supply1 vddR;

rBIST BT(BISTFlag, hnl_309, hnl_310, hnl_311, hnl_312, SCANOut, BISTMode, IOSTMode, RData1[0], RData0[0], Reset, Synint, hnl_313, hnl_314, hnl_315);
rRACC RC(hnl_313, SynClk, SynClkFd, Synint, hnl_316, hnl_317, hnl_318, hnl_319, hnl_320, hnl_321, hnl_322, hnl_323, hnl_324, hnl_325, hnl_326, hnl_314, hnl_327, hnl_328, hnl_329, BCSel[3], BCSel[2],
BCSel[1], BCSel[0], BDSel[3], BDSel[2], BDSel[1], BDSel[0], BESel[3], BESel[2], BESel[1], BESel[0], BusClk, ByPSel, ByPass, CCtlLd, PhStall, PwrUp, RCSel[3], RCSel[2], RCSel[1], RCSel[0], RDSel[3],
RDSel[2], RDSel[1], RDSel[0], Reset, SCANClk, SCANEn, SCANMode, StopR, StopT, SynClkIn, hnl_330, hnl_311, hnl_331, rclkASIC, hnl_332, tclkASIC);
rRACL RL(ReqEn, Transmit, hnl_330, RData7[9], RData6[9], RData5[9], RData4[9], RData3[9], RData2[9], RData1[9], RData0[9], hnl_331, RData7[4], RData6[4], RData5[4], RData4[4], RData3[4], RData2[4],
RData1[4], RData0[4], RData7[3], RData6[3], RData5[3], RData4[3], RData3[3], RData2[3], RData1[3], RData0[3], RData7[2], RData6[2], RData5[2], RData4[2], RData3[2], RData2[2], RData1[2], RData0[2],
RData7[1], RData6[1], RData5[1], RData4[1], RData3[1], RData2[1], RData1[1], RData0[1], RData7[0], RData6[0], RData5[0], RData4[0], RData3[0], RData2[0], RData1[0], RData0[0], hnl_315, BusCtrl,
BusData[4], BusData[3], BusData[2], BusData[1], BusData[0], Reset, Synint, Vref, hnl_311, TData7[9], TData6[9], TData5[9], TData4[9], TData3[9], TData2[9], TData1[9], TData0[9], CCtlO[5], CCtlO[4],
CCtlO[3], CCtlO[2], CCtlO[1], CCtlO[0], hnl_312, hnl_318, hnl_319, hnl_321, hnl_322, hnl_323, hnl_324, hnl_325, hnl_313, hnl_326, hnl_314, hnl_328, hnl_333, hnl_334, hnl_329, TData7[4], TData6[4],
TData5[4], TData4[4], TData3[4], TData2[4], TData1[4], TData0[4], TData7[3], TData6[3], TData5[3], TData4[3], TData3[3], TData2[3], TData1[3], TData0[3], TData7[2], TData6[2], TData5[2], TData4[2],
TData3[2], TData2[2], TData1[2], TData0[2], TData7[1], TData6[1], TData5[1], TData4[1], TData3[1], TData2[1], TData1[1], TData0[1], TData7[0], TData6[0], TData5[0], TData4[0], TData3[0], TData2[0],
TData1[0], TData0[0]);
rCCtrl CC(CCtlO[5], CCtlO[4], CCtlO[3], CCtlO[2], CCtlO[1], CCtlO[0], hnl_335, CCtlEn, CCtlI[5], CCtlI[4], CCtlI[3], CCtlI[2], CCtlI[1], CCtlI[0], CCtlPgm, hnl_316, hnl_330, hnl_317, hnl_322, Reset,
hnl_313, hnl_314, hnl_336, hnl_327);
rRACR RR(BusEnable, RData7[8], RData6[8], RData5[8], RData4[8], RData3[8], RData2[8], RData1[8], RData0[8], RData7[7], RData6[7], RData5[7], RData4[7], RData3[7], RData2[7], RData1[7], RData0[7],
RData7[6], RData6[6], RData5[6], RData4[6], RData3[6], RData2[6], RData1[6], RData0[6], RData7[5], RData6[5], RData5[5], RData4[5], RData3[5], RData2[5], RData1[5], RData0[5], hnl_332, hnl_336,
hnl_333, hnl_334, BusData[8], BusData[7], BusData[6], BusData[5], ExtBE, hnl_330, hnl_311, TData7[10], TData6[10], TData5[10], TData4[10], TData3[10], TData2[10], TData1[10], TData0[10], CCtlO[5], CCtlO[4],
CCtlO[3], CCtlO[2], CCtlO[1], CCtlO[0], hnl_319, hnl_320, hnl_321, hnl_323, hnl_325, hnl_313, hnl_326, hnl_314, hnl_335, SCANIn, hnl_309, hnl_310, hnl_329, TData7[8], TData6[8], TData5[8], TData4[8],
TData3[8], TData2[8], TData1[8], TData0[8], TData7[7], TData6[7], TData5[7], TData4[7], TData3[7], TData2[7], TData1[7], TData0[7], TData7[6], TData6[6], TData5[6], TData4[6], TData3[6], TData2[6],
TData1[6], TData0[6], TData7[5], TData6[5], TData5[5], TData4[5], TData3[5], TData2[5], TData1[5], TData0[5]);
endmodule