test1.m
3.56 KB
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// This test checks out the synchronous opeartion of RAC
// This is a very simple test that shows the things required
// to initialize the RAC cell.
module test();
reg Vref;
reg BusClk;
reg [10:0] TData7, TData6, TData5, TData4, TData3, TData2, TData1, TData0;
reg [3:0] BDSel, BCSel, BESel, RDSel, RCSel;
reg ShrtClks;
reg Reset, SOutI, SIn;
reg PwrUp, ExtBE, StopR, StopT;
reg BISTMode, IOSTMode, SCANMode, SCANClk, SCANEn, SCANIn;
reg CCtlEn, CCtlLd, CCtlPgm;
reg [5:0] CCtlI;
reg ByPass, ByPSel, rclkASIC, tclkASIC, PhStall;
wire [8:0] BusData;
wire SynClk, BusControl, BusEnable, SOut, SynClkIn;
wire [9:0] RData7, RData6, RData5, RData4, RData3, RData2, RData1, RData0;
wire ReqEn, DoneReq, RetryReq, SInI;
wire BISTFlag, SCANOut;
supply1 vdd;
supply0 gnd;
rac R(RData7, RData6, RData5, RData4, RData3, RData2, RData1, RData0,
SynClk, SynClkFd,
SOut, BusEnable, SInI, BISTFlag, SCANOut,
BusCtrl, BusData,
BusClk, BDSel, BCSel, BESel, RDSel, RCSel,
Reset,
TData7, TData6, TData5, TData4, TData3, TData2, TData1, TData0,
SIn, SOutI, Vref,
BISTMode, IOSTMode, SCANMode, SCANClk, SCANEn, SCANIn, SynClkIn,
CCtlEn, CCtlLd, CCtlI, CCtlPgm, PwrUp, ExtBE, StopR, StopT,
ByPass, ByPSel, rclkASIC, tclkASIC, PhStall);
// pull ups for the Rambus wires
rtranif0 i10(BusEnable, vdd, gnd);
rtranif0 i9(BusCtrl, vdd, gnd);
rtranif0 i8(BusData[8], vdd, gnd);
rtranif0 i7(BusData[7], vdd, gnd);
rtranif0 i6(BusData[6], vdd, gnd);
rtranif0 i5(BusData[5], vdd, gnd);
rtranif0 i4(BusData[4], vdd, gnd);
rtranif0 i3(BusData[3], vdd, gnd);
rtranif0 i2(BusData[2], vdd, gnd);
rtranif0 i1(BusData[1], vdd, gnd);
rtranif0 i0(BusData[0], vdd, gnd);
// Gr_waves
initial
begin
`include "waves.v"
end
// Power hook ups
initial
begin
// Power hook ups
Vref = 1;
CCtlPgm = 1;
// Mode signals
PwrUp = 1;
StopR = 0;
StopT = 0;
PhStall = 0;
// Test Inputs
BISTMode = 0;
IOSTMode = 0;
SCANMode = 0;
SCANEn = 0;
SCANClk = 0;
SCANIn = 0;
ByPass = 0;
ByPSel = 0;
tclkASIC = 0;
rclkASIC = 0;
ExtBE = 0;
end
// BusClk generation
initial
begin
BusClk = 1;
end
always #20 BusClk = ~BusClk;
// SynClk Generation. Initially SynClkIn is driven from
// outside to get rid of unknown states in SynClk circuit
assign SynClkIn = (ShrtClks == 1) ? SynClk : ShrtClks;
// Reset + current control
initial
begin
ShrtClks = 0;
#1400;
ShrtClks = 1;
Reset = 1;
#810;
Reset = 0;
CCtlEn = 0;
CCtlLd = 0;
CCtlI = 6'b111111;
#5600;
CCtlLd = 1;
// Reset = 1;
#320;
CCtlLd = 0;
// Reset = 0;
#4000;
$stop;
end
// Other inputs
initial
begin
// initial data
TData7 = 0;
TData6 = 3;
TData5 = 7;
TData4 = 5;
TData3 = 2;
TData2 = 1;
TData1 = 4;
TData0 = 9;
// Select values
BDSel = 1;
BCSel = 1;
BESel = 1;
RDSel = 4;
RCSel = 4;
// Serial ports
SIn = 0;
SOutI = 0;
// changing the BDSel, BCSel, BESel and RDSel values
#8400; BDSel = 8; BDSel = 8; BDSel = 8; RDSel = 4; RCSel = 4;
#800; BDSel = 1; BDSel = 1; BDSel = 1; RDSel = 8; RCSel = 8;
#800; BDSel = 2; BDSel = 2; BDSel = 2; RDSel = 2; RCSel = 2;
#800; BDSel = 0; BDSel = 0; BDSel = 0; RDSel = 1; RCSel = 1;
end
always @ (posedge SynClk) TData7 = TData7 + 43;
always @ (posedge SynClk) TData6 = TData6 + 27;
always @ (posedge SynClk) TData5 = TData5 + 11;
always @ (posedge SynClk) TData4 = TData4 + 68;
always @ (posedge SynClk) TData3 = TData3 + 54;
always @ (posedge SynClk) TData2 = TData2 + 39;
always @ (posedge SynClk) TData1 = TData1 + 5;
always @ (posedge SynClk) TData0 = TData0 + 72;
endmodule