verilog.log
1.65 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Host command: /usr/verilog/hppa_9.0_1.6c.5/tools.hppa/vtools/vlog/exe/verilogrs
Command arguments:
-f /usr/verilog/hppa_9.0_1.6c.5/tools.hppa/vtools/vlog/exe/pass.f
+host:snakes9
-f inc.file
test1.m
rac.w5.A
VERILOG-XL 1.6c.5 log file created May 17, 1994 14:57:03
* Copyright Cadence Design Systems, Inc. 1985, 1988. *
* All Rights Reserved. Licensed Software. *
* Confidential and proprietary information which is the *
* property of Cadence Design Systems, Inc. *
*********************************************************
* *
* WARNING : +speedup WAS NOT USED ON THE COMMAND LINE *
* *
* In order to obtain maximum behavioral simulation *
* performance use +speedup on the command line. *
* This will become the default in future releases. *
* *
*********************************************************
Compiling source file "test1.m"
Compiling included source file "waves.v"
Continuing compilation of source file "test1.m"
Compiling source file "rac.w5.A"
GRAPHICS 4.2.2 Mon Jun 14 19:48:14 PDT 1993 (rancho)
Highest level modules:
test
L115 "test1.m": $stop at simulation time 12130
Type ? for help
C1 > $finsh;
Error! Task or function ($finsh) not defined [Verilog-TOFD]
Command 1:
C1 > $finish;
C1: $finish at simulation time 12130
1609529 simulation events
CPU time: 0.3 secs to compile + 2.4 secs to link + 56.4 secs in simulation
End of VERILOG-XL 1.6c.5 May 17, 1994 14:58:31