cc_edge_div.synscr
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#!/bin/csh -f
#
# ASICSYN
#
# Phil Gossett
# 7/23/94
#
vlsishell << EOF
set echo on
asicsyn
#
# default flags
set hdl verilog
set autowrite false
set automaticanswer no
#
# verilog sources
#
load [v]cc_edge_div
#
# load constraint file
load [cmd]cc_edge_div_cons
synthesize
write
show cellhier
report
qtv
show simparms
trace critical
exit
exit
exit
EOF
#