set linelimit 10000
load [nls]vusl_f schematic
load [nle]vusl layout
set output vusl_netcomp_err
equiv s:bulk s:*.bulk
equiv l:bulk l:*.bulk
equiv l:vss1 l:bulk
equiv s:vss s:bulk
equiv l:clk l:clk$*
equiv l:vct_rfadrt_vt1_rd[0] l:vct_rfadrt_vt1_rd[0]$*
st S:*.*.n1234 l:*.core.core1.*w.c.n1234
st *vdpaccmidzerowb.w0.b2.dpbnf_c1 *core.core1.vdpaccmidzerowb.b2W.dptnf_c1

auto
id
check
show unidentified
show unexamined
show worst