set linelimit 10000
load [nls]vusl schematic
load [nle]vusl_p layout
set output vusl_netcomp_err
equiv s:bulk s:*.bulk
equiv l:bulk l:*.bulk
equiv l:vss1 l:bulk
equiv s:vss s:bulk
equiv L:clk L:clk$*
equiv L:vct_incrci0_ac L:vct_incrci0_ac$*
equiv L:vdp_addupci0_ac L:vdp_addupci0_ac$*
equiv L:vdp_cslwco0_ac L:vdp_cslwco0_ac$*
equiv L:vct_fdaddci0_ac L:vct_fdaddci0_ac$*
equiv L:vct_alucin0_mu L:vct_alucin0_mu$*
equiv L:vct_incrci1_ac L:vct_incrci1_ac$*
equiv L:vdp_addlwco1_ac L:vdp_addlwco1_ac$*
equiv L:vdp_cslwco1_ac L:vdp_cslwco1_ac$*
equiv L:vct_addlwci1_ac L:vct_addlwci1_ac$*
equiv L:vct_alucin1_mu L:vct_alucin1_mu$*
equiv L:vct_rfadrt_vt1_rd[0] L:vct_rfadrt_vt1_rd[0]$*
auto
id
check
show unidentified
show unexamined
show worst