ms_sc.ss
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/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = ms_sc
wire_load = 256000
standard_load = 0.01
clock = clock
clocks = { clock gclock }
default_input_delay = 1.5
default_output_delay = 13.0
default_input_load = 20
default_output_load = 20
default_drive_cell = dfntnh
default_drive_pin = q
default_period = 16.0
default_max_transition = 1.5
default_uncertainty = 1.0
/*****************************************************************************/
/* set the path and read */
/*****************************************************************************/
search_path = search_path + "../src" + "../../syn" + "../../inc"
read -f verilog module + .v
current_design = module
/*****************************************************************************/
/* default environment */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/*****************************************************************************/
/* clock constraints */
/*****************************************************************************/
create_clock clocks -period default_period -waveform {0.0 default_period / 2 }
set_clock_skew -uncertainty default_uncertainty clocks
set_dont_touch_network clocks
/*****************************************************************************/
/* default constraints */
/*****************************************************************************/
set_max_area 0
set_dont_touch { ne35hd130d/nt01d* }
set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null
set_drive 0 { clock reset_l }
set_input_delay 0 clocks
set_false_path -from reset_l
set_max_transition default_max_transition current_design
/*****************************************************************************/
/* custom constraints */
/*****************************************************************************/
set_output_delay 4.0 -clock clock { rdramlen }
set_output_delay 4.0 -clock clock { rdramaddr }
set_output_delay 4.0 -clock clock { rdramrw }
set_output_delay 7.0 -clock clock { rdspace }
set_output_delay 10.0 -clock clock { rdramreq }
set_output_delay 9.0 -clock clock { rdramdir }
set_output_delay 10.0 -clock clock { rbzrptr }
set_output_delay 10.0 -clock clock { rdxdec }
set_output_delay 10.0 -clock clock { stallwrctxt }
set_output_delay 10.0 -clock clock { stallrdctxt }
set_output_delay 10.0 -clock clock { wrcxi }
set_output_delay 10.0 -clock clock { rdcxi }
/*****************************************************************************/
/* check */
/*****************************************************************************/
link
check_design > module + ".lint"
/*****************************************************************************/
/* compile */
/*****************************************************************************/
compile
compile -ungroup_all -incremental
/*****************************************************************************/
/* write */
/*****************************************************************************/
include "report.dc"
change_names -rules compass_rules -hierarchy
write -format edif -hierarchy -o module + ".edf" module
write -format db -hierarchy -o module + ".db" module
quit