set_input_delay 8.0 -clock clk {reset_l};
set_input_delay 2.5 -clock clk {halt};
set_input_delay 4.0 -clock clk {iddq_test};

set_input_delay 13.0 -clock clk {rd_base};
set_input_delay 12.0 -clock clk {rd_offset};
set_input_delay 8.0 -clock clk {rd_elem_num};
set_input_delay 2.0 -clock clk {elem_num};
set_input_delay 11.0 -clock clk {branch_or_addr}; 
set_input_delay 2.0 -clock clk {df_ls_drive_ls_in_wb};
set_input_delay 2.0 -clock clk {df_pass_thru};
set_input_delay 2.0 -clock clk {su_ex_store};
set_input_delay 2.0 -clock clk {su_ex_load};
set_input_delay 2.0 -clock clk {vu_ex_store};
set_input_delay 2.0 -clock clk {vu_ex_load};
set_input_delay 2.0 -clock clk {ex_mtc2};
set_input_delay 2.0 -clock clk {ex_mfc2};
set_input_delay 2.0 -clock clk {ex_cfc2};
set_input_delay 2.0 -clock clk {cp0_write};	/* from Jeff */
set_input_delay 13.0 -clock clk {vu_rd_ld_dec_k};
set_input_delay 13.0 -clock clk {vu_rd_st_dec_k};
set_input_delay 8.0 -clock clk {chip_sel};
set_input_delay 2.0 -clock clk {ex_su_byte_ls};
set_input_delay 2.0 -clock clk {ex_su_half_ls};
set_input_delay 2.0 -clock clk {ex_su_uns_ls};
set_input_delay 2.0 -clock clk {ex_dma_rd_to_dm};
set_input_delay 2.0 -clock clk {ex_dma_dm_to_rd};
set_input_delay 4.0 -clock clk {dma_wen}; 
set_input_delay 1.5 -clock clk {dma_address};	/* from Jeff */
/* removed since internal - set_input_delay 1.5 -clock clk {dmem_dataout}; */
set_input_delay 9.0 -clock clk {mem_write_data};
set_input_delay 2.0 -clock clk {ex_mfc0};
set_input_delay 2.0 -clock clk {pc};
 
set_input_delay 4.0 -clock clk {ls_data};
set_input_delay 8.0 -clock clk {cp0_data};	/* from Jeff */

/* removed since internal - set_driving_cell -cell ni01d5 -pin z {dmem_dataout}; */

set_output_delay -max 2.0 -clock clk {vu_bwe};
/* removed since internal - set_output_delay -max 8.0 -clock clk {df_chip_sel_l}; */
/* removed since internal - set_output_delay -max 10.0 -clock clk {df_wen_l}; */
/* removed since internal - set_output_delay -max 11.0 -clock clk {df_addr_low}; */
/* removed since internal - set_output_delay -max 8.5 -clock clk {df_addr_high}; */
set_output_delay -max 9.0 -clock clk {dmem_rd_data};
/* removed since internal - set_output_delay -max 4.0 -clock clk {df_datain}; */
/* removed since unused - set_output_delay -max 2.5 -clock clk {debug_df_dma_rd_to_dm}; */

set_output_delay -max 3.0 -clock clk {ls_data};
set_output_delay -max 8.0 -clock clk {cp0_data}; /* from Jeff */

group_path -name non_dmem_rd_group -to all_outputs();
group_path -default -to {dmem_rd_data, ls_data};
group_path -name dmem_rd_group -to {dmem_rd_data};
group_path -name ls_data_group -to {ls_data};