si_control.v
29.8 KB
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//vi: set tabstop=4 shiftwidth=4 wrapmargin=4:
/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: si_control.v,v 1.1.1.1 2002/05/17 06:07:48 blythe Exp $
module si_control (clk,
reset_l,
dbus_enable,
dma_grant,
dma_start,
write_data,
reg_address,
io_address,
write_enable,
div_cnt,
pch_rsp_reg,
pch_rsp_reg_d1,
pch_reg_msb,
pch_cmd_valid,
dma_req,
dma_read,
dma_adrs,
dma_length,
read_data,
interrupt,
io_busy,
dbus_data);
`include "si.vh"
// in out list
// global inputs
input clk;
input reset_l;
// pchclk inputs
input [1:0] div_cnt;
// CBUS inputs
input [SI_REG_WRITE_SIZE-1:0] write_data;
input [SI_IO_ADDRESS_SIZE-1:2] io_address; // 2 lsbs not used
input [SI_REG_ADDRESS_SIZE-1:0] reg_address;
input write_enable;
input dma_grant;
input dma_start;
inout [63:0] dbus_data;
input dbus_enable;
// CBUS outputs
output [31:0] read_data;
output dma_read ;
output io_busy;
output [6:0] dma_length;
output dma_req;
output interrupt;
output [DRAM_ADDRESS_SIZE-1:0] dma_adrs;
// pchannel io
input pch_rsp_reg;
input pch_rsp_reg_d1;
output pch_reg_msb;
output pch_cmd_valid;
// output regs
reg [31:0] read_data; // psuedo reg
reg dma_read;
reg io_busy;
reg interrupt;
reg dma_req;
reg dma_state_busy_d1;
reg pch_cmd_valid ;
reg [21:0] dram_adrs; // word aligned address reg
// confirm dma_length size is 7 bits;
reg [6:0] dma_length;
// output psudo reg
reg [DRAM_ADDRESS_SIZE-1: 0] dma_adrs;
wire pch_reg_msb;
// internal psuedo reg for address incrementor
reg [21:0] dram_increment;
// internal psuedo reg
wire dma_state_busy;
wire pch_phase1;
reg next_dma_busy;
reg next_io_busy;
reg [12:0] pif_status;
//internal regs
reg [8:0] pif_adrs;
reg [31:0] pch_reg; // shift reg
reg [63:0] data_reg;
reg [2:0] pch_operation;
reg [8:0] pch_cnt;
reg [31:0] write_reg;
reg new_cmd;
reg inc_dram_adrs;
// psuedo reg
reg load_dram_adrs;
reg dma_start_reg;
reg dma_error;
reg read_pending;
reg dma_busy;
//internal pchannel regs
wire pch_rsp_reg;
wire pch_rsp_reg_d1;
// DMA control regs
// for now assume DMA STATE size is 4 bits
// dma_state
parameter DMA_IDLE = 4'h0,
WAIT_PIF_RD = 4'h1,
DMA_WR_REQ = 4'h2,
WAIT_WR_START = 4'h3,
DMA_RD_REQ = 4'h4,
DMA_RD_XFER = 4'h5,
WAIT_NEXT_DMA = 4'h6,
WAIT_PCH_DONE = 4'h7,
PIF_RD_CPU = 4'h8,
PIF_RD_CPU_FINISH = 4'h9,
IO_WRITE = 4'ha,
WAIT_IO_WR_DONE = 4'hb;
// dreg_sel_upr dreg_sel_lwr
parameter DREG = 0,
PCHREG = 1,
DBUSREG = 2,
WDATA = 3;
reg [3:0] dma_state ;
reg pch_word_avail;
reg begin_pif_read;
reg begin_pif_write;
reg [3:0] dma_cnt ;
reg [1:0] dreg_sel_upr;
reg [1:0] dreg_sel_lwr;
reg dma_word_avail;
reg pch_reg_avail;
// pch_operation
parameter WR64B = 3'b000,
RD64B = 3'b001,
WR4B = 3'b010,
RD4BCPU = 3'b111;
// PCH State machine controls
reg [3:0] pch_state;
// pch_state
parameter PCH_IDLE = 4'h0,
PCH_RD_ADRS = 4'h1,
PCH_SHF_RD_ADRS = 4'h3,
PCH_WAIT_RD_ACK = 4'h4,
PCH_RD_DATA = 4'h5,
PCH_WAIT_WR_DATA = 4'h6,
PCH_WR_ADRS = 4'h7,
PCH_SHF_WR_ADRS = 4'h8,
PCH_WAIT_WR_ACK = 4'h9,
PCH_WR_START = 4'ha,
PCH_WR_DATA = 4'hb;
reg [3:0] pch_action;
// Controls for pch_reg shift register
// pch_action
parameter HOLD = 3'd0,
LD_CMD_ADRS = 3'd1,
SHIFT = 3'd2,
LD_LSB = 3'd3,
LD_MSB = 3'd4;
// decode the div_cnt register to determine pchannel phase
// div_cnt comparator
assign pch_phase1 = (div_cnt == 2'b01);
//////////////////////////////////////////////////////////////////////
// --- dma_state
//
// Master Control State Machine "dma_state"
//
always @(posedge clk or negedge reset_l) begin
if (reset_l == 1'b0) begin
dma_state[3:0] <= DMA_IDLE;
dma_req <= 0;
pch_state[3:0] <= PCH_IDLE;
// flops that are dont care during reset
pch_action <= 4'bxxxx;
pch_word_avail <= 1'bx;
inc_dram_adrs <= 1'bx;
dma_req <= 1'bx;
dma_read <= 1'bx;
dreg_sel_upr <= 2'bxx;
dreg_sel_lwr <= 2'bxx;
dma_word_avail <= 1'bx;
begin_pif_read <= 1'bx;
begin_pif_write <= 1'bx;
dma_cnt <= 4'bxxxx;
dma_req <= 0;
dma_read <= 0;
pch_reg_avail <= 1'bx;
pch_cmd_valid <= 1'bx;
pch_cnt <= 9'bxxxxxxxxx;
end
else if (reset_l == 1'b1) begin // not reset
case (dma_state) // synopsys full_case parallel_case
DMA_IDLE: begin
pch_word_avail <= 0;
inc_dram_adrs <= 0;
dma_req <= 0;
dma_read <= 0;
dreg_sel_upr <= DREG;
dreg_sel_lwr <= DREG;
dma_word_avail <= 0;
if (new_cmd && (pch_operation == RD64B)) begin
dma_state <= WAIT_PIF_RD;
begin_pif_read <= 1;
begin_pif_write <= 0;
dma_cnt <= 4'hf;
end
else if (new_cmd && (pch_operation == WR4B)) begin
dma_state <= IO_WRITE;
begin_pif_write <= 1;
begin_pif_read <= 0;
dma_cnt <= 4'h0;
end
else if ( new_cmd && (pch_operation == WR64B)) begin
dma_state <= DMA_RD_REQ;
begin_pif_write <= 1;
begin_pif_read <= 0;
dma_cnt <= 4'h7; // #64 bit dma words -1
end
else if (new_cmd && (pch_operation == RD4BCPU)) begin
dma_state <= PIF_RD_CPU;
dma_cnt <= 0;
begin_pif_read <= 1;
begin_pif_write <= 0;
end
else begin
begin_pif_read <= 0;
begin_pif_write <= 0;
dma_state <= dma_state;
end
end // DMA_IDLE
WAIT_PIF_RD: begin
inc_dram_adrs <= 0;
dma_req <= 0;
dma_read <= 0;
if (pch_word_avail) begin
pch_word_avail <= 0;
if (pch_operation == RD64B) begin
if (dma_cnt[0] == 1) begin
// first 32 of 64 bits available
// latch 32 msbs and go wait for next 32 bits.
dreg_sel_upr <= PCHREG;
dreg_sel_lwr <= DREG;
dma_state <= WAIT_PIF_RD;
dma_cnt <= dma_cnt -1;
end
else if (dma_cnt[0] == 0) begin
// second 32 of 64 bits avail, grab em and send to dram
// dont decrement count here, need to evaluate it
// later after the write
dreg_sel_lwr <= PCHREG;
dma_state <= DMA_WR_REQ;
end
end
end // if pch_word_avail
else begin // pch_word not avail
dreg_sel_lwr <= DREG;
dreg_sel_upr <= DREG;
end
end // begin
DMA_WR_REQ: begin
inc_dram_adrs <= 0;
dreg_sel_upr <= DREG;
dreg_sel_lwr <= DREG;
dma_read <= 0;
// request write dma
if (!dma_req)
begin
dma_req <= 1;
end
else if (dma_req)
begin
if (dma_grant)
begin
dma_req <= 0;
dma_state<= WAIT_WR_START;
end
else if (!dma_grant)
begin
dma_req <= 1;
end
end
end // begin
WAIT_WR_START: begin
// Hazard here: the dma write must complete before the pch shift
// for the next 32 bit word completes or data will be overwritten
// in the data_register. this is guaranteed by si dbus priority.
dma_read <= 0;
dma_req <= 0;
dreg_sel_upr <= DREG;
dreg_sel_lwr <= DREG;
if (dma_start_reg) begin
if (dma_cnt[3:0] == 0) begin
dma_state <= DMA_IDLE;
inc_dram_adrs <= 0;
end
else if (dma_cnt [3:0] != 0) begin
dma_cnt <= dma_cnt -1; // ready count for next word
inc_dram_adrs <= 1;
dma_state <= WAIT_PIF_RD;
end
end
end // WAIT_WR_START
DMA_RD_REQ: begin
dma_read <= 1;
inc_dram_adrs <= 0;
// request read dma
if (!dma_req) begin
dma_req <= 1;
dreg_sel_upr <= DREG;
dreg_sel_lwr <= DREG;
end
// dma request in process, wait for grant
else if (dma_req) begin
if (dma_grant) begin
dma_req <= 0;
dma_state <= DMA_RD_XFER;
dreg_sel_upr <= DREG; // Requires min time from grant to start
dreg_sel_lwr <= DREG;
end
else if (!dma_grant) begin
dma_req <= 1; // continue request
dreg_sel_upr <= DREG;
dreg_sel_lwr <= DREG;
end
end
end // DMA_RD_REQ
DMA_RD_XFER: begin
dma_read <= 1;
dma_req <= 0;
if (dma_start) begin
dreg_sel_upr <= DBUSREG; // read the dbus 1 clock only
dreg_sel_lwr <= DBUSREG;
dma_word_avail <= 1;
if (dma_cnt == 0) begin
dma_state <= WAIT_PCH_DONE;
inc_dram_adrs <= 0 ;
end
else begin // dma_cnt != 0
dma_cnt <= dma_cnt -1;
dma_state <= WAIT_NEXT_DMA;
inc_dram_adrs <= 1; // inc for next transfer
end
end // dma_start
else begin // !dma_start
dreg_sel_upr <= DREG;
dreg_sel_lwr <= DREG;
inc_dram_adrs <= 0;
end
end // DMA_RD_XFER
WAIT_NEXT_DMA: begin
dma_req <= 0;
dma_read <= 1;
dreg_sel_upr <= DREG;
dreg_sel_lwr <= DREG;
inc_dram_adrs <= 0;
if (pch_reg_avail) begin
dma_state <= DMA_RD_REQ;
pch_reg_avail <= 0;
end
end
WAIT_PCH_DONE: begin
dreg_sel_upr <= DREG;
dreg_sel_lwr <= DREG;
dma_req <= 0;
dma_read <= 1;
inc_dram_adrs <= 0;
if (pch_reg_avail) begin
dma_state <= DMA_IDLE;
pch_reg_avail <= 0;
end
end
PIF_RD_CPU: begin
inc_dram_adrs <= 0;
dma_req <= 0;
dma_read <= 0;
if (pch_word_avail) begin
pch_word_avail <= 0;
dreg_sel_upr <= PCHREG;
dreg_sel_lwr <= PCHREG;
dma_state <= PIF_RD_CPU_FINISH;
end // if pch_word_avail
else begin // pch_word not avail
dreg_sel_lwr <= DREG;
dreg_sel_upr <= DREG;
end
end // PIF_RD_CPU
PIF_RD_CPU_FINISH: begin
inc_dram_adrs <= 0;
dma_read <= 0;
dma_req <= 0;
dreg_sel_upr <= DREG;
dreg_sel_lwr <= DREG;
dma_state <= DMA_IDLE;
end // PIF_RD_CPU_FINISH
IO_WRITE: begin
dma_read <= 0;
inc_dram_adrs <= 0;
dma_req <= 0;
dreg_sel_upr <= DREG;
dreg_sel_lwr <= WDATA; // load io write data to data reg 31:0
dma_state <= WAIT_IO_WR_DONE;
end // IO_WRITE
WAIT_IO_WR_DONE: begin
dreg_sel_upr <= DREG;
dreg_sel_lwr <= DREG;
dma_req <= 0;
dma_read <= 0;
inc_dram_adrs <= 0;
if (pch_reg_avail) begin
dma_state <= DMA_IDLE;
pch_reg_avail <= 0;
end
end // WAIT_IO_WR_DONE
default: begin
dma_state <= 4'hx;
pch_word_avail <= 'bx;
inc_dram_adrs <= 'bx;
dma_req <= 'bx;
dma_read <= 'bx;
dreg_sel_upr <= 2'bx;
dreg_sel_lwr <= 2'bx;
dma_word_avail <= 'bx;
begin_pif_read <= 'bx;
begin_pif_write <= 'bx;
dma_cnt <= 4'hx;
end // default
endcase
//////////////////////////////////////////////////////////////////////
// --- pch_state
// PCH Control State Machine "pch_state"
//
//
//
case (pch_state) // synopsys full_case parallel_case
PCH_IDLE: begin
pch_action <= HOLD;
pch_reg_avail <= 0;
pch_cmd_valid <= 0;
if (begin_pif_read) begin
pch_state <= PCH_RD_ADRS;
begin_pif_read <= 0;
end
if (begin_pif_write) begin
begin_pif_write <= 0;
if (pch_operation == WR4B) begin
pch_state <= PCH_WR_ADRS;
end
else begin
pch_state <= PCH_WAIT_WR_DATA;
end
end
end
PCH_RD_ADRS: begin
if (pch_phase1) begin
pch_action <= LD_CMD_ADRS;
pch_state <= PCH_SHF_RD_ADRS;
pch_cnt <= 9'd11;
pch_cmd_valid <= 1;
end
else begin
pch_action <= HOLD;
pch_cmd_valid <= 0;
end
end
PCH_SHF_RD_ADRS: begin
if (pch_phase1) begin
// when done shifting address
if (pch_cnt == 0) begin
pch_state <= PCH_WAIT_RD_ACK;
pch_action <= HOLD;
pch_cmd_valid <= 0;
if (pch_operation == RD4BCPU) begin
pch_cnt <= 9'd31;
end
if (pch_operation == RD64B) begin
pch_cnt <= 9'd511;
end
end
else begin
pch_action <= SHIFT;
pch_cnt <= pch_cnt -1;
pch_cmd_valid <= 1;
end
end
else begin
pch_action <= HOLD;
pch_cmd_valid <= 1;
end
end // PCH_SHF_RD_ADRS
PCH_WAIT_RD_ACK: begin
pch_action <= HOLD;
pch_cmd_valid <= 0;
if (pch_phase1) begin
// look for ack return from PIF
if (pch_rsp_reg_d1 && ~pch_rsp_reg ) begin // hi to lo edge
pch_state <= PCH_RD_DATA;
end
end
end // PCH_WAIT_RD_ACK
PCH_RD_DATA: begin
if (pch_phase1) begin
if (pch_cnt [4:0] == 0) begin
pch_word_avail <= 1;
pch_action <= SHIFT;
if (pch_cnt[8:5] == 0) begin
pch_state <= PCH_IDLE;
end
else begin
pch_cnt <= pch_cnt -1;
end
end
else begin
pch_cnt <= pch_cnt -1;
pch_action <= SHIFT;
end
end
else pch_action <= HOLD;
pch_cmd_valid <= 0; // unconditionally during this state
end // PCH_RD_DATA
PCH_WAIT_WR_DATA: begin
pch_action <= HOLD;
pch_cmd_valid <= 0;
if (dma_word_avail) begin
dma_word_avail <= 0;
pch_state <= PCH_WR_ADRS;
end
end
PCH_WR_ADRS: begin
if (pch_phase1) begin
pch_action <= LD_CMD_ADRS;
pch_state <= PCH_SHF_WR_ADRS;
pch_cnt <= 9'd11;
pch_cmd_valid <= 1;
end
else begin
pch_action <= HOLD;
pch_cmd_valid <= 0;
end
end
PCH_SHF_WR_ADRS: begin
if (pch_phase1) begin
// when done shifting address
if (pch_cnt == 0) begin
pch_state <= PCH_WAIT_WR_ACK;
pch_action <= HOLD;
pch_cmd_valid <= 0;
if (pch_operation == WR4B) begin
pch_cnt <= 9'd31;
end
if (pch_operation == WR64B) begin
pch_cnt <= 9'd511;
end
end
else begin
pch_cmd_valid <= 1;
pch_action <= SHIFT;
pch_cnt <= pch_cnt -1;
end
end
else begin
pch_action <= HOLD;
pch_cmd_valid <= 1;
end
end // PCH_SHF_WR_ADRS
PCH_WAIT_WR_ACK: begin
if (pch_phase1) begin
// look for ack return from PIF
if (pch_rsp_reg_d1 && ~pch_rsp_reg ) begin // hi to lo edge
pch_state <= PCH_WR_START;
pch_action <= LD_CMD_ADRS ; // to get "start" into the channel
pch_cmd_valid <= 1;
end
else begin
pch_action <= HOLD;
pch_cmd_valid <= 0;
end
end
else begin
pch_action <= HOLD;
pch_cmd_valid <= 0;
end
end // PCH_WAIT_WR_ACK
PCH_WR_START: begin
pch_cmd_valid <= 1;
if (pch_phase1) begin
pch_state <= PCH_WR_DATA;
if (pch_operation == WR4B) begin
pch_action <= LD_LSB; // io write, load from data reg 31:0
end
else begin
// for 64 bit writes, shift MSB word first
pch_action <= LD_MSB ;
end
end
else pch_action <= HOLD;
end // PCH_WR_START
PCH_WR_DATA: begin
if (pch_phase1) begin
pch_cnt <= pch_cnt -1;
// if down-count is on a 32 bit boundary
if (pch_cnt [4:0] == 0) begin
// if more 64 bit dmas are needed
if (pch_cnt[8:6] != 0) begin
// if 64 bit boundary
pch_cmd_valid <= 1;
if (pch_cnt[5] == 0) begin
pch_action <= LD_MSB;
end
// 32 bit boundary
// on 32 bit boundary, download the lsb reg
// to the shift reg and request next dma read
// transfer
else if (pch_cnt [5] == 1) begin
pch_action <= LD_LSB;
pch_reg_avail <= 1; // causes read dma request
end
end // [8:6] != 0
else begin // no more dmas to be perfomed
if (pch_cnt[5] == 1) begin
// last 32 bits
pch_action <= LD_LSB;
pch_cmd_valid <= 1;
end
else if (pch_cnt[5] == 0) begin
// count == 0, all done
pch_state <= PCH_IDLE;
pch_reg_avail <= 1; // causes dma to idle
pch_cmd_valid <= 0;
pch_action <= HOLD;
end
end
end // [4:0] == 0
else begin // not 32 bit boundary
pch_action <= SHIFT;
pch_cmd_valid <= 1;
end
end //pch_phase1
else begin
pch_action <= HOLD;
pch_cmd_valid <= 1;
end
end // PCH_WR_DATA
default: begin
pch_state <= 4'hx;
pch_cnt <= 9'hx;
pch_action <= 3'bx;
pch_reg_avail <= 'bx;
pch_cmd_valid <= 'bx;
end // default
endcase
end // not reset
end // always
//////////////////////////////////////////////////////////////////////
// --- cbus interface control and datapath block
//
//
// CBUS interface Datapath and control
//
//
//
assign dma_state_busy = (dma_state != 0);
always @ (posedge clk or negedge reset_l) begin
if (reset_l == 1'b0) begin
dma_error <= 0;
interrupt <= 0;
read_pending <= 0;
io_busy <= 1'bx;
dma_busy <= 1'bx;
dram_adrs <= 22'bx ;
pif_adrs <= 9'bxxxxxxxxx;
pch_operation <= 3'bx ;
dma_length <= 7'bxxxxxxx;
dma_start_reg <= 1'bx;
new_cmd <= 1'bx;
dma_state_busy_d1 <= 1'bx;
write_reg <= 32'bx;
end
else begin
// new_cmd indicates the start of a PChannel operation
// requested from the CBUS interface. new_cmd is pulsed here
// to kick off dma_state machine. there is no handshake coming back.
// note: if dma_busy is set and a new dma is requested, the new
// dma is ignored and the current dma is satisfied, and a dma_error
// flag is set.
// if current action is io read, the cpu is hung awaiting read response
// so no similar checks for io_busy are required.
// if dma_busy and a io read is requested, the io read is set pending
// the dma in progress should complete. One hazard is the
// io_read request will overwrite the pif address register. If the
// current dma has not yet used the pif address, incorrect dma
// data will result.
next_dma_busy = 0; // initial condition for psuedo reg
next_io_busy = 0; // initial condition for psuedo reg
load_dram_adrs = 0; // initial condition for psuedo reg
dram_increment = 0; // initial condition for psuedo reg
if (dma_state_busy == 1) begin
new_cmd <= 0;
// maintain busy's from dma_state machine here.
// io_writes set dma_busy and io_busy to allow
// dma_busy to generate interrupt at end of io write
if ((dma_state == PIF_RD_CPU) | (dma_state == PIF_RD_CPU_FINISH)) begin
next_io_busy = 1;
end
else if ((dma_state == IO_WRITE) | (dma_state == WAIT_IO_WR_DONE)) begin
next_io_busy = 1;
next_dma_busy = 1;
end
else begin // for all other dma_states
next_dma_busy = 1;
end
// for all dma_states
if (read_pending) begin
next_io_busy = 1; // maintain io busy if read pending
end
if (write_enable) begin
if (reg_address == 5) begin
// read request overlapping dma in progress
// set pending read request,
// continue the dma in progress
// the pif requires to run through completion.
pif_adrs <= io_address [10:2] ; // possible hazzard to current dma
next_io_busy = 1; // read busy must be held until read complete
read_pending <= 1; // hold the read request
end
else if (reg_address == 0 | reg_address == 1 |
reg_address == 2 | reg_address == 4 ) begin
// illegal write set error flag, hold current states
dma_error <= 1;
end
end // if write enable
end // dma state busy
else if (dma_state_busy == 0) begin // dma_state is idle
// pending requests are served ahead of simultaneous write requests
if (read_pending) begin // service the pending read request
new_cmd <= 1;
pch_operation <= RD4BCPU;
read_pending <= 0;
next_io_busy = 1;
next_dma_busy = 0;
end
// write_enbles cant happen when reads are pending
else if (write_enable ) begin // not read pending
read_pending <= 0;
if (reg_address == 0) begin
load_dram_adrs = 1; // load dram address from write data
new_cmd <= 0;
next_dma_busy = 0;
next_io_busy = 0;
end
else if (reg_address == 1) begin // RD64B
pch_operation <= RD64B;
pif_adrs <= write_data [10:2]; // aligned on word address
new_cmd <= 1;
dma_length <= 7'd7;
next_dma_busy = 1;
next_io_busy = 0;
end
else if (reg_address == 2) begin // WR4B
pch_operation <= WR4B;
write_reg <= write_data ;
pif_adrs <= io_address [10:2] ; // word align io address
new_cmd <= 1;
// dma_length is not needed for io writes
next_io_busy = 1;
next_dma_busy = 1; // dma_busy to generate interrupt
end
else if (reg_address == 4) begin // WR64B
pch_operation <= WR64B;
pif_adrs <= write_data [10:2]; // aligned on word address
new_cmd <= 1;
dma_length <= 7'd7;
next_dma_busy = 1;
next_io_busy = 0;
end
else if (reg_address == 5) begin // RD4BCPU
pch_operation <= RD4BCPU;
pif_adrs <= io_address [10:2] ; // word align io address
new_cmd <= 1;
// dma_length is not needed for reads
next_io_busy = 1;
next_dma_busy = 0;
end
end // if write enable
else if (write_enable == 0) begin // idle and not write_enable
dma_length <= dma_length;
if (read_pending) begin // service the pending read request
new_cmd <= 1;
pch_operation <= RD4BCPU;
read_pending <= 0;
next_io_busy = 1;
next_dma_busy = 0;
end
else if ( !read_pending) begin
if (new_cmd == 1) begin
if (dma_busy) next_dma_busy = 1;
if (io_busy) next_io_busy = 1;
new_cmd <= 0; // was set, so clear it.
end
else if (new_cmd == 0) begin // nothing is going on or just entered idle
next_dma_busy = 0;
next_io_busy = 0; // io_read occurs on this transition
new_cmd <= 0;
end
end // else if !read_pending
end // else if write enable = 0
end // dma idle
// control the interrupt flag.
// if set and clear overlap, leave it set
dma_state_busy_d1 <= dma_state_busy;
if ((dma_state_busy == 0) && (dma_state_busy_d1 != 0) && (dma_busy == 1)) begin
interrupt <= 1;
end
else if (write_enable && (reg_address == 6)) begin
interrupt <= 0; // clear interrupt flag
end
dma_start_reg <= dma_start;
dma_busy <= next_dma_busy; // latch the psuedo reg
io_busy <= next_io_busy; // latch the psuedo reg
// dram_address counter
// increment dram adrs on 64 bit boundary
// under control of dma control state machine.
// load dram adrs on non-registsed address load signal
dram_increment = dram_adrs + (inc_dram_adrs << 1) ;
case (load_dram_adrs) // synopsys full_case parallel_case
0: dram_adrs <= dram_increment;
1: dram_adrs <= write_data >> 2;
endcase
end // not reset
end // always
always @ (interrupt or dma_state or pch_state or dma_error or read_pending or io_busy or dma_busy ) begin
pif_status = { interrupt, dma_state,pch_state, dma_error, read_pending, io_busy,dma_busy};
end // always
// non registered read_data mux
always @ (reg_address or dram_adrs or pif_adrs or pif_status or data_reg ) begin
read_data = 0; // initial condition for psuedo reg
case (reg_address) // synopsys full_case parallel_case
0:
read_data = {dram_adrs, 2'b0}; // fill to byte address
1:
read_data = {pif_adrs, 2'b00}; // fill to byte address
2:
read_data = data_reg[31:0];
4:
read_data = {pif_adrs, 2'b00}; // fill to byte address
5:
read_data = data_reg[31:0]; // non-registered
6:
read_data = pif_status; // non-registered
endcase
dma_adrs = {dram_adrs, 2'b0}; // non registerd byte address
end // always
//////////////////////////////////////////////////////////////////////
// --- dbus datapath block
//
// DBUS interface Datapath
//
//
always @ (posedge clk) begin
case (dreg_sel_upr) // synopsys full_case parallel_case
DREG: data_reg [ 63:32] <= data_reg[63:32];
PCHREG: data_reg [ 63:32] <= pch_reg[31:0];
DBUSREG: data_reg [ 63:32] <= dbus_data[63:32];
2'd3: data_reg [ 63:32] <= 32'bx;
default: data_reg [ 63:32] <= 32'bx;
endcase
case (dreg_sel_lwr) // synopsys full_case parallel_case
DREG: data_reg [ 31:0] <= data_reg[31:0];
PCHREG: data_reg [ 31:0] <= pch_reg[31:0];
DBUSREG: data_reg [ 31:0] <= dbus_data[31:0];
WDATA: data_reg [ 31:0] <= write_reg[31:0];
default: data_reg [ 31:0] <= 32'bx;
endcase
end // always
//////////////////////////////////////////////////////////////////////
// --- pch_reg shift register
//
//
//
// shift reg multiplexing
always @(posedge clk) begin
// 32 bit serial input/output shift register
case (pch_action) // synopsys full_case parallel_case
SHIFT : pch_reg <= {pch_reg[30:0] , pch_rsp_reg}; // left shift
LD_LSB : pch_reg <= data_reg[31:0]; // load lsbs
LD_MSB : pch_reg <= data_reg[63:32]; // load msbs
HOLD : pch_reg <= pch_reg ; // hold current value
// start bit, 2bit op, 9 bit address
LD_CMD_ADRS : pch_reg[31:20] <= {1'b0, pch_operation[1:0], pif_adrs[8:0]};
endcase
end // always
assign pch_reg_msb = pch_reg[31];
//////////////////////////////////////////////////////////////////////
// --- databus instantiation
//
//
// instantiate data_bus = data_reg if dbus_enable here
dbus_driver dbus_driver_0(
.dbus_data_out(data_reg),
.dbus_enable(dbus_enable),
.dbus_data(dbus_data)
);
endmodule