/*
*************************************************************************
*									*
*               Copyright (C) 1994, Silicon Graphics, Inc.		*
*									*
*  These coded instructions, statements, and computer programs  contain	*
*  unpublished  proprietary  information of Silicon Graphics, Inc., and	*
*  are protected by Federal copyright  law.  They  may not be disclosed	*
*  to  third  parties  or copied or duplicated in any form, in whole or	*
*  in part, without the prior written consent of Silicon Graphics, Inc.	*
*									*
*************************************************************************
*/

// $Id: 

// vt_decode.v:	vt register address decode, 5->32,

`timescale 1ns / 10ps

module vt_decode(
		  vt_rd_inst_h,
		  vt_rd_inst_l,
		  vt_else,

		  vt_rd_inst_h_sel,
		  vt_rd_inst_l_sel,
		  branch_or_addr_unbuf,
		  su_inst_6_unbuf,
		  su_inst_15_unbuf,

		  vt_decoded_a,
		  vt_decoded_b,
		  branch_or_addr,
		  su_inst_6,
		  su_inst_15
		);

input [4:0] vt_rd_inst_h;
input [4:0] vt_rd_inst_l;
input [4:0] vt_else;

input vt_rd_inst_h_sel;
input vt_rd_inst_l_sel;
input [11:0] branch_or_addr_unbuf;
input su_inst_6_unbuf;
input su_inst_15_unbuf;

output [31:0] vt_decoded_a;	// vt_decoded_a and vt_decoded_b are identical.
output [31:0] vt_decoded_b;	// Duplication is for timing/loading reasons.
output [11:0] branch_or_addr;
input su_inst_6;
input su_inst_15;


wire [31:0] vt_rd_inst_h_dec_b;
wire [31:0] vt_rd_inst_l_dec_b;
wire [31:0] vt_else_dec_b;
wire [1:0] sb;

decode_5x32  vt_rd_inst_h_dec(
			       .rNum(vt_rd_inst_h),
			       .rNumdecode_b(vt_rd_inst_h_dec_b)
			     );
decode_5x32  vt_rd_inst_l_dec(
			       .rNum(vt_rd_inst_l),
			       .rNumdecode_b(vt_rd_inst_l_dec_b)
			     );
decode_5x32       vt_else_dec(
			       .rNum(vt_else),
			       .rNumdecode_b(vt_else_dec_b)
			     );

wire vt_rd_inst_h_sel_buf_l; 
wire vt_rd_inst_l_sel_buf_l;

in01d5 vt_sb_0(.zn(sb[0]), .i(vt_rd_inst_h_sel));
in01d5 vt_sb_1(.zn(sb[1]), .i(vt_rd_inst_l_sel));

vt_mux4x1_8	vt_decoded_0(.zb_a(vt_decoded_a[7:0]),
			     .zb_b(vt_decoded_b[7:0]),
			     .i0(vt_else_dec_b[7:0]),
			     .i1(vt_rd_inst_h_dec_b[7:0]),
			     .i2(vt_rd_inst_l_dec_b[7:0]),
			     .i3(8'hfe),
			     .sb(sb)
			    );
vt_mux4x1_8	vt_decoded_1(.zb_a(vt_decoded_a[15:8]),
			     .zb_b(vt_decoded_b[15:8]),
			     .i0(vt_else_dec_b[15:8]),
			     .i1(vt_rd_inst_h_dec_b[15:8]),
			     .i2(vt_rd_inst_l_dec_b[15:8]),
			     .i3(8'hff),
			     .sb(sb)
			    );
vt_mux4x1_8	vt_decoded_2(.zb_a(vt_decoded_a[23:16]),
			     .zb_b(vt_decoded_b[23:16]),
			     .i0(vt_else_dec_b[23:16]),
			     .i1(vt_rd_inst_h_dec_b[23:16]),
			     .i2(vt_rd_inst_l_dec_b[23:16]),
			     .i3(8'hff),
			     .sb(sb)
			    );
vt_mux4x1_8	vt_decoded_3(.zb_a(vt_decoded_a[31:24]),
			     .zb_b(vt_decoded_b[31:24]),
			     .i0(vt_else_dec_b[31:24]),
			     .i1(vt_rd_inst_h_dec_b[31:24]),
			     .i2(vt_rd_inst_l_dec_b[31:24]),
			     .i3(8'hff),
			     .sb(sb)
			    );

ni01d5 br_buf_00(.i(branch_or_addr_unbuf[0]), .z(branch_or_addr[0]));
ni01d5 br_buf_01(.i(branch_or_addr_unbuf[1]), .z(branch_or_addr[1]));
ni01d5 br_buf_02(.i(branch_or_addr_unbuf[2]), .z(branch_or_addr[2]));
ni01d5 br_buf_03(.i(branch_or_addr_unbuf[3]), .z(branch_or_addr[3]));
ni01d5 br_buf_04(.i(branch_or_addr_unbuf[4]), .z(branch_or_addr[4]));
ni01d5 br_buf_05(.i(branch_or_addr_unbuf[5]), .z(branch_or_addr[5]));
ni01d5 br_buf_06(.i(branch_or_addr_unbuf[6]), .z(branch_or_addr[6]));
ni01d5 br_buf_07(.i(branch_or_addr_unbuf[7]), .z(branch_or_addr[7]));
ni01d5 br_buf_08(.i(branch_or_addr_unbuf[8]), .z(branch_or_addr[8]));
ni01d5 br_buf_09(.i(branch_or_addr_unbuf[9]), .z(branch_or_addr[9]));
ni01d5 br_buf_10(.i(branch_or_addr_unbuf[10]), .z(branch_or_addr[10]));
ni01d5 br_buf_11(.i(branch_or_addr_unbuf[11]), .z(branch_or_addr[11]));

ni01d5 su_inst_buf_6(.i(su_inst_6_unbuf), .z(su_inst_6));
ni01d5 su_inst_buf_15(.i(su_inst_15_unbuf), .z(su_inst_15));

endmodule


module vt_mux4x1_8(zb_a, zb_b, i0, i1, i2, i3, sb);
input [7:0] i0, i1, i2, i3;
input [1:0] sb;
output [7:0] zb_a;
output [7:0] zb_b;

wire [7:0] z;
wire s0, s1;

in01d5 u_s0(.zn(s0), .i(sb[0]));
in01d5 u_s1(.zn(s1), .i(sb[1]));

mx41d2 u_00(.z(z[ 0]),.i0(i0[ 0]),.i1(i1[ 0]),.i2(i2[ 0]),.i3(i3[ 0]),.s0(s0),.s1(s1));
mx41d2 u_01(.z(z[ 1]),.i0(i0[ 1]),.i1(i1[ 1]),.i2(i2[ 1]),.i3(i3[ 1]),.s0(s0),.s1(s1));
mx41d2 u_02(.z(z[ 2]),.i0(i0[ 2]),.i1(i1[ 2]),.i2(i2[ 2]),.i3(i3[ 2]),.s0(s0),.s1(s1));
mx41d2 u_03(.z(z[ 3]),.i0(i0[ 3]),.i1(i1[ 3]),.i2(i2[ 3]),.i3(i3[ 3]),.s0(s0),.s1(s1));
mx41d2 u_04(.z(z[ 4]),.i0(i0[ 4]),.i1(i1[ 4]),.i2(i2[ 4]),.i3(i3[ 4]),.s0(s0),.s1(s1));
mx41d2 u_05(.z(z[ 5]),.i0(i0[ 5]),.i1(i1[ 5]),.i2(i2[ 5]),.i3(i3[ 5]),.s0(s0),.s1(s1));
mx41d2 u_06(.z(z[ 6]),.i0(i0[ 6]),.i1(i1[ 6]),.i2(i2[ 6]),.i3(i3[ 6]),.s0(s0),.s1(s1));
mx41d2 u_07(.z(z[ 7]),.i0(i0[ 7]),.i1(i1[ 7]),.i2(i2[ 7]),.i3(i3[ 7]),.s0(s0),.s1(s1));

in01d5 u_zb00(.zn(zb_a[0]), .i(z[0]));
in01d5 u_zb01(.zn(zb_b[0]), .i(z[0]));

in01d5 u_zb10(.zn(zb_a[1]), .i(z[1]));
in01d5 u_zb11(.zn(zb_b[1]), .i(z[1]));

in01d5 u_zb20(.zn(zb_a[2]), .i(z[2]));
in01d5 u_zb21(.zn(zb_b[2]), .i(z[2]));

in01d5 u_zb30(.zn(zb_a[3]), .i(z[3]));
in01d5 u_zb31(.zn(zb_b[3]), .i(z[3]));

in01d5 u_zb40(.zn(zb_a[4]), .i(z[4]));
in01d5 u_zb41(.zn(zb_b[4]), .i(z[4]));

in01d5 u_zb50(.zn(zb_a[5]), .i(z[5]));
in01d5 u_zb51(.zn(zb_b[5]), .i(z[5]));

in01d5 u_zb60(.zn(zb_a[6]), .i(z[6]));
in01d5 u_zb61(.zn(zb_b[6]), .i(z[6]));

in01d5 u_zb70(.zn(zb_a[7]), .i(z[7]));
in01d5 u_zb71(.zn(zb_b[7]), .i(z[7]));


endmodule

module decode_5x32 (rNum, rNumdecode_b);

	input	[4:0]	rNum ;
	output	[31:0]	rNumdecode_b ;

	wire	[7:0]	dec_enable ;
	wire	rNumbuf1 ;
	wire	rNumbuf2 ;
	wire	rNumbufcopy1 ;
	wire	rNumbufcopy2 ;


	dc38d2 rf_decode_1ststg (
				  .a0 (rNum[0]), .a1 (rNum[3]), .a2 (rNum[4]),
				  .z0n	(dec_enable[0]), .z1n (dec_enable[1]),
				  .z2n	(dec_enable[2]), .z3n (dec_enable[3]),
				  .z4n	(dec_enable[4]), .z5n (dec_enable[5]),
				  .z6n	(dec_enable[6]), .z7n (dec_enable[7])
				);

	ni01d5	address_buf2	(
				  .i (rNum[2]),	.z (rNumbuf2)
				);

	ni01d5	address_buf1	(
				  .i (rNum[1]),	.z (rNumbuf1)
				);

	ni01d5	address_bufcopy2 (
				  .i (rNum[2]),	.z (rNumbufcopy2)
				);

	ni01d5	address_bufcopy1 (
				  .i (rNum[1]),	.z (rNumbufcopy1)
				);

	de24d2	rf_decode_0to6	(
				  .a0 (rNumbuf1), .a1 (rNumbuf2), .en (dec_enable[0]),
				  .z0n (rNumdecode_b[0]),	.z1n (rNumdecode_b[2]),
				  .z2n (rNumdecode_b[4]),	.z3n (rNumdecode_b[6])
				);

	de24d2	rf_decode_1to7	(
				  .a0 (rNumbuf1), .a1 (rNumbuf2), .en (dec_enable[1]),
				  .z0n (rNumdecode_b[1]),	.z1n (rNumdecode_b[3]),
				  .z2n (rNumdecode_b[5]),	.z3n (rNumdecode_b[7])
				);

	de24d2	rf_decode_8to14	(
				  .a0 (rNumbuf1), .a1 (rNumbuf2), .en (dec_enable[2]),
				  .z0n (rNumdecode_b[8]),	.z1n (rNumdecode_b[10]),
				  .z2n (rNumdecode_b[12]),	.z3n (rNumdecode_b[14])
				);

	de24d2	rf_decode_9to15 (
				  .a0 (rNumbuf1), .a1 (rNumbuf2), .en (dec_enable[3]),
				  .z0n (rNumdecode_b[9]),	.z1n (rNumdecode_b[11]),
				  .z2n (rNumdecode_b[13]),	.z3n (rNumdecode_b[15])
				);

	de24d2	rf_decode_16to22 (
				  .a0 (rNumbufcopy1), .a1 (rNumbufcopy2), .en (dec_enable[4]),
				  .z0n (rNumdecode_b[16]),	.z1n (rNumdecode_b[18]),
				  .z2n (rNumdecode_b[20]),	.z3n (rNumdecode_b[22])
				);

	de24d2	rf_decode_17to23 (
				  .a0 (rNumbufcopy1), .a1 (rNumbufcopy2), .en (dec_enable[5]),
				  .z0n (rNumdecode_b[17]),	.z1n (rNumdecode_b[19]),
				  .z2n (rNumdecode_b[21]),	.z3n (rNumdecode_b[23])
				);

	de24d2	rf_decode_24to30 (
				  .a0 (rNumbufcopy1),  .a1 (rNumbufcopy2),  .en (dec_enable[6]),
				  .z0n (rNumdecode_b[24]),	.z1n (rNumdecode_b[26]),
				  .z2n (rNumdecode_b[28]),	.z3n (rNumdecode_b[30])
				);

	de24d2	rf_decode_25to31 (
				  .a0 (rNumbufcopy1), .a1 (rNumbufcopy2), .en (dec_enable[7]),
				  .z0n (rNumdecode_b[25]),	.z1n (rNumdecode_b[27]),
				  .z2n (rNumdecode_b[29]),	.z3n (rNumdecode_b[31])
				);

endmodule