module = syn_clk_buf

search_path = search_path + "../src" + "../../inc" + \
   "../../../lib/verilog/user" + "../../syn"

/* read the verilog netlist */
read -f verilog ../src/syn_clk_buf.v

current_design = syn_clk_buf

link 

check_design > syn_clk_buf.lint

/* enforce naming restrictions for Compass tools */
change_names -rules compass_rules -hierarchy

report_reference

write -f edif -o syn_clk_buf.edf -hier syn_clk_buf

quit