/* set up a new search path */
search_path = search_path + "../../inc" + "../../syn"

/* read the verilog sources */
read -f verilog ../src/tc_adrs.v

current_design = tc_adrs

/* set timing constraints */
set_operating_conditions NOM
set_wire_load 256000 -mode top

max_area 0

create_clock gclk -period 16.0 -waveform {0.0 8.0}
set_clock_skew -uncertainty 1.0 gclk

set_input_delay 1.5 -clock gclk all_inputs()
set_output_delay 13.0 -clock gclk all_outputs()
set_driving_cell -cell dfntnh -pin q all_inputs();
set_max_transition 1.5 current_design
set_load 0.20 { all_inputs() all_outputs() }

set_input_delay 0 gclk
set_drive 0 { gclk }
set_dont_touch_network { gclk }

link 

check_design > tc_adrs.lint

/*  hack to get around synopsys bug  */
get_license Designware-Basic

compile -map_effort high -ungroup_all

report_reference
report_constraint -all_violators

module = tc_adrs
include "report.dc"

write -f edif -o tc_adrs.edf -hier tc_adrs
write -f db -o tc_adrs.db

quit