/* setup aliases */

alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
				        set_wire_load 256000 -mode top;"
alias set_default_timing_constraints "create_clock clk -period 12.0 -waveform {0 6.0}; \
				      set_input_delay 2.0 -clock clk all_inputs(); \
				      set_output_delay 2.0 -clock clk all_outputs(); \
				      max_delay 2.0 -to all_outputs(); \
				      set_load 0.2 all_outputs();"

/* set up a new search path */
search_path = search_path + "../../inc"

/* read the verilog sources */
read -f verilog ../src/ram_bist_tmem.v




current_design = ram_bist_tmem

set_default_operating_conditions
set_default_timing_constraints

set_driving_cell -none { clk }
set_drive 0 { clk }
set_dont_touch_network { clk }
set_arrival 0 clk

set_max_fanout 0.02 reset_l

set_dont_use {ne35hd130d/mbnfnq ne35hd130d/mbnfnr}
max_area 0

/* new contraints to bring ramp times down */
/*
set_max_transition 1.5 current_design
set_load 20 * 0.01 all_outputs() > /dev/null
set_output_delay 10.0 -clock clk \
{bist_done bist0_fail bist1_fail bist2_fail bist3_fail bist4_fail bist5_fail bist6_fail bist7_fail}
*/
set_register_type -exact -flip_flop dfntnh { find (cell,"bist_done_reg") }
set_register_type -exact -flip_flop dfntnh { find (cell,"bist0_fail_reg") }
set_register_type -exact -flip_flop dfntnh { find (cell,"bist1_fail_reg") }
set_register_type -exact -flip_flop dfntnh { find (cell,"bist2_fail_reg") }
set_register_type -exact -flip_flop dfntnh { find (cell,"bist3_fail_reg") }
set_register_type -exact -flip_flop dfntnh { find (cell,"bist4_fail_reg") }
set_register_type -exact -flip_flop dfntnh { find (cell,"bist5_fail_reg") }
set_register_type -exact -flip_flop dfntnh { find (cell,"bist6_fail_reg") }
set_register_type -exact -flip_flop dfntnh { find (cell,"bist7_fail_reg") }

link 

check_design > ram_bist_tmem.lint

compile -map_effort high -ungroup_all

report -reference

report_constraint -all_violators

write -f edif -o ram_bist_tmem.edf -hier ram_bist_tmem

quit