tm_load.ss
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/* setup aliases */
alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
set_wire_load 128000 -mode top;"
alias set_default_timing_constraints "create_clock gclk -period 14.0 -waveform {0 8.0}; \
set_input_delay 4.0 -clock gclk all_inputs(); \
set_output_delay 2.0 -clock gclk all_outputs(); \
max_delay 12.0 -to all_outputs(); \
set_load 0.2 all_outputs();"
/* set up a new search path */
search_path = search_path + "../../inc"
/* read the verilog sources */
read -f verilog ../src/tm_load.v
current_design = tm_load
/* max_area 800 */
set_default_operating_conditions
set_default_timing_constraints
set_driving_cell -none { gclk }
set_drive 0 { gclk }
set_dont_touch_network { gclk }
set_arrival 0 gclk
set_dont_use {ne35hd130d/mbnfnq ne35hd130d/mbnfnr}
max_area 0
link
check_design > tm_load.lint
compile -map_effort high -ungroup_all
report -reference
report_constraint -all_violators
write -f edif -o tm_load.edf -hier tm_load
quit