/************************************************************************\
 |                                                                        |
 |               Copyright (C) 1994, Silicon Graphics, Inc.               |
 |                                                                        |
 |  These coded instructions, statements, and computer programs  contain  |
 |  unpublished  proprietary  information of Silicon Graphics, Inc., and  |
 |  are protected by Federal copyright  law.  They  may not be disclosed  |
 |  to  third  parties  or cosied or duplicated in any form, in whole or  |
 |  in part, without the prior written consent of Silicon Graphics, Inc.  |
 |                                                                        |
 \************************************************************************/

// $Id: vi_controller.v,v 1.1.1.1 2002/05/17 06:07:49 blythe Exp $

////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module:	vi_controller
// description:	DMA request FSM for video interface.
//
// designer:	Phil Gossett
// date:	1/3/95
//
////////////////////////////////////////////////////////////////////////

module vi_controller(clk, reset_l,
   dma_grant, dma_start, dma_last,
   reg_write_data, reg_address, reg_write_enable, v_current,
   block_address, block_length, block_word, bank_sel,
   block_start, block_count, read_addr, pre_int,
   horizontal_flag, di, dout_a, dout_b,
   block_partial, wen_a, wen_b, addr_a, addr_b, do,
   dma_address, dma_length, dma_request, block_grant, reg_read_data,
   vbus_clock_enable_l, ctrl, origin, width, v_int,
   hsync_width, burst_width, vsync_width, burst_start,
   v_sync_period, h_sync_period, leap_pattern,
   hsync_leap_b, hsync_leap_a, h_video_end, h_video_start,
   v_video_end, v_video_start, v_burst_end, v_burst_start,
   x_scale, y_scale, x_offset, y_offset, vi_int, refresh_strobe);

`include "vi.vh"

input clk;                                   // system clock
input reset_l;                               // system reset_l
input dma_grant;                             // grant the DMA operation
input dma_start;                             // start the DMA operation
input dma_last;                              // end the DMA operation
input [CBUS_DATA_SIZE-1:0] reg_write_data;   // register write data from cbus
input [VI_REG_ADDRESS_SIZE-1:0] reg_address; // register read/write address
input reg_write_enable;                      // register write enable
input [9:0] v_current;			     // lines read only reg
input [DRAM_ADDRESS_SIZE-1:0] block_address;
input [DMA_LENGTH_SIZE-1:0] block_length;
input [3:0] block_word;                      // location in span buffers
input bank_sel;				     // buffer bank select
input block_start;			     // treat as consecutive req's
input [1:0] block_count;		     // number of consec req's - 1
input [3:0] read_addr;			     // buffer read address
input pre_int;                               // for synchronization
input horizontal_flag;                       // for refresh strobe
input [EBUS_DATA_SIZE+DBUS_DATA_SIZE-1:0] di;
input [EBUS_DATA_SIZE+DBUS_DATA_SIZE-1:0] dout_a;
input [EBUS_DATA_SIZE+DBUS_DATA_SIZE-1:0] dout_b;

output block_partial;                        // some partially covered
output wen_a;                                // buffer write enable
output wen_b;                                // buffer write enable
output [3:0] addr_a;
output [3:0] addr_b;
output [EBUS_DATA_SIZE+DBUS_DATA_SIZE-1:0] do;
output [DRAM_ADDRESS_SIZE-1:0] dma_address;
output [DMA_LENGTH_SIZE-1:0] dma_length;
output dma_request;                          // request a DMA read cycle
output block_grant;
output [CBUS_DATA_SIZE-1:0] reg_read_data;   // read data to cbus
output vbus_clock_enable_l;
output [15:0] ctrl;		// bits
output [23:0] origin;		// bytes
output [11:0] width;		// pixels
output [9:0] v_int;		// half lines
output [7:0] hsync_width;	// pixels
output [7:0] burst_width;	// pixels
output [3:0] vsync_width;	// pixels
output [9:0] burst_start;	// pixels
output [9:0] v_sync_period;	// half lines
output [11:0] h_sync_period;	// clocks
output [4:0] leap_pattern;	// fields
output [11:0] hsync_leap_b;	// clocks
output [11:0] hsync_leap_a;	// clocks
output [9:0] h_video_end;	// pixels
output [9:0] h_video_start;	// pixels
output [9:0] v_video_end;	// half lines
output [9:0] v_video_start;	// half lines
output [9:0] v_burst_end;	// half lines
output [9:0] v_burst_start;	// half lines
output [11:0] x_scale;		// 2.10
output [11:0] y_scale;		// 2.10
output [11:0] x_offset;		// 2.10
output [11:0] y_offset;		// 2.10
output vi_int;				// synchronized interrupt
output refresh_strobe;			// synchronized refresh request

// output registers
reg block_partial;
reg dma_request;
reg block_grant;
reg [15:0] ctrl;		// bits
reg [23:0] origin;		// bytes
reg [11:0] width;		// pixels
reg [9:0] v_int;		// half lines
reg [7:0] hsync_width;		// pixels
reg [7:0] burst_width;		// pixels
reg [3:0] vsync_width;		// pixels
reg [9:0] burst_start;		// pixels
reg [9:0] v_sync_period;	// half lines
reg [11:0] h_sync_period;	// clocks
reg [4:0] leap_pattern;		// fields
reg [11:0] hsync_leap_b;	// clocks
reg [11:0] hsync_leap_a;	// clocks
reg [9:0] h_video_end;		// pixels
reg [9:0] h_video_start;	// pixels
reg [9:0] v_video_end;		// half lines
reg [9:0] v_video_start;	// half lines
reg [9:0] v_burst_end;		// half lines
reg [9:0] v_burst_start;	// half lines
reg [11:0] x_scale;		// 2.10
reg [11:0] y_scale;		// 2.10
reg [11:0] x_offset;		// 2.10
reg [11:0] y_offset;		// 2.10
reg vi_int;
reg refresh_strobe;

wire block_start_1d;	// instanciated synchronizer delay
wire block_start_2d;
wire block_start_3d;
wire pre_int_1d;
wire pre_int_2d;
wire pre_int_3d;
wire horizontal_flag_1d;
wire horizontal_flag_2d;
wire horizontal_flag_3d;

reg refresh_strobe_0d;
reg refresh_strobe_1d;
reg refresh_strobe_2d;
reg refresh_strobe_3d;
reg refresh_strobe_4d;
reg refresh_strobe_5d;
reg block_start_4d;	// for edge detectors
reg block_start_4e;
reg pre_int_4d;
reg horizontal_flag_4d;
reg dma_grant_1d;	// to widen strobe for other clock domain
reg dma_start_1d;	// delay line
reg dma_start_2d;
reg dma_start_3d;
reg dma_start_4d;
reg dma_last_1d;
reg dma_last_2d;
reg dma_last_3d;
reg dma_last_4d;
reg dma_last_5d;
reg [3:0] block_word_1d;
reg [3:0] block_word_2d;
reg [3:0] block_length_1d;
reg [3:0] block_length_2d;
reg [3:0] span_addr;    	// address for spanbuf read
reg [1:0] span_count;		// number of remaining consecutive spans
reg [1:0] dma_count;		// number of remaining consecutive dma's
reg [9:0] v_current_safe;	// synchronized sample of current line
reg [6:0] test_addr;		// spanbuf diagnostic address override
reg [EBUS_DATA_SIZE+DBUS_DATA_SIZE-1:0] staged_data; // diagnostic write data
reg pre_wen_a;
reg pre_wen_b;
reg [3:0] span_length;
reg split_last;
reg granted;

wire split;
wire [DRAM_ADDRESS_SIZE-1:0] block_end;
wire [DRAM_ADDRESS_SIZE-1:0] split_addr;
wire [3:0] paddr_a;
wire [3:0] paddr_b;
wire [CBUS_DATA_SIZE-1:0] test_data;
wire partial;

assign block_end = block_address + block_length;
assign split_addr = block_end & 24'hFFF800;
assign split = block_address[11] ^ block_end[11];
assign dma_address = (split && split_last) ? split_addr :
					     block_address;
assign dma_length  =  split ? (split_last ?
					(block_end  - split_addr) :
					(split_addr - block_address - 1)) :
			      block_length;
assign partial = (!ctrl[0] && ((di[56:54] != 3'b111) || // 16 bit 5/5/5/3
                               (di[38:36] != 3'b111) ||
                               (di[20:18] != 3'b111) ||
                               (di[2:0]   != 3'b111))) ||
                 ( ctrl[0] && ((di[45:43] != 3'b111) || // 32 bit 8/8/8/8
                               (di[9:7]   != 3'b111)));
assign wen_a   = !ctrl[7] ? pre_wen_a : ((test_addr[1:0] == 3) &&
					 !test_addr[6] &&
					 (reg_address == 15) &&
					  reg_write_enable);
assign wen_b   = !ctrl[7] ? pre_wen_b : ((test_addr[1:0] == 3) &&
					  test_addr[6] &&
					 (reg_address == 15) &&
					  reg_write_enable);
assign paddr_a = bank_sel ? read_addr : span_addr;
assign paddr_b = bank_sel ? span_addr : read_addr;
assign addr_a  = !ctrl[7] ? paddr_a   : test_addr[5:2];
assign addr_b  = !ctrl[7] ? paddr_b   : test_addr[5:2];
assign do      = !ctrl[7] ? di        : staged_data;
assign test_data =
	!test_addr[6] ?
		(!test_addr[1] ?
			(!test_addr[0] ?
				{dout_a[ 71: 56], dout_a[ 53: 38]} :
				{dout_a[ 35: 20], dout_a[ 17:  2]} ) :
			(!test_addr[0] ?
				{dout_a[ 55: 54], dout_a[ 37: 36],
				 dout_a[ 19: 18], dout_a[  1:  0]} :
				0 )) :
		(!test_addr[1] ?
			(!test_addr[0] ?
				{dout_b[ 71: 56], dout_b[ 53: 38]} :
				{dout_b[ 35: 20], dout_b[ 17:  2]} ) :
			(!test_addr[0] ?
				{dout_b[ 55: 54], dout_b[ 37: 36],
				 dout_b[ 19: 18], dout_b[  1:  0]} :
				0 )) ;

// instanciated synchronizer flops
dfntnb bbsy1 (.cp(clk), .d(block_start),    .q(block_start_1d));
dfntnb bbsy2 (.cp(clk), .d(block_start_1d), .q(block_start_2d));
dfntnb bbsy3 (.cp(clk), .d(block_start_2d), .q(block_start_3d));
dfntnb hfsy1 (.cp(clk), .d(horizontal_flag),    .q(horizontal_flag_1d));
dfntnb hfsy2 (.cp(clk), .d(horizontal_flag_1d), .q(horizontal_flag_2d));
dfntnb hfsy3 (.cp(clk), .d(horizontal_flag_2d), .q(horizontal_flag_3d));
dfntnb pisy1 (.cp(clk), .d(pre_int),    .q(pre_int_1d));
dfntnb pisy2 (.cp(clk), .d(pre_int_1d), .q(pre_int_2d));
dfntnb pisy3 (.cp(clk), .d(pre_int_2d), .q(pre_int_3d));

// state machine
reg [1:0] state;
parameter
	STATE_IDLE           = 0,	
	STATE_READ_REQ       = 1,
	STATE_READ_WAIT      = 2,
	STATE_READ           = 3;

always @(posedge clk or negedge reset_l)
   begin
   if (!reset_l)
      begin
      // resetable registers
      dma_request <= 0;
      block_partial <= 0;
      split_last <= 0;
      granted <= 0;
      pre_wen_a <= 0;
      pre_wen_b <= 0;
      pre_int_4d <= 0;
      block_start_4d <= 0;
      block_start_4e <= 0;
      ctrl <= 0;			// blank video (incl syncs)
      hsync_width   <=  8'd1;		// for refresh
      h_sync_period <= 12'd2047;	// for refresh
      v_int <= 'h3FF;
      vi_int <= 0;
      refresh_strobe_0d <= 0;
      refresh_strobe_1d <= 0;
      refresh_strobe_2d <= 0;
      refresh_strobe_3d <= 0;
      refresh_strobe_4d <= 0;
      refresh_strobe_5d <= 0;
      refresh_strobe <= 0;
      state <= STATE_IDLE;
      block_grant <= 0;
      origin <= 0;
      width <= 0;
      burst_width <= 0;
      vsync_width <= 0;
      burst_start <= 0;
      v_sync_period <= 0;
      leap_pattern <= 0;
      hsync_leap_b <= 0;
      hsync_leap_a <= 0;
      h_video_end <= 0;
      h_video_start <= 0;
      v_video_end <= 0;
      v_video_start <= 0;
      v_burst_end <= 0;
      v_burst_start <= 0;
      x_scale <= 0;
      y_scale <= 0;
      x_offset <= 0;
      y_offset <= 0;
      horizontal_flag_4d <= 0;
      dma_grant_1d <= 0;
      dma_start_1d <= 0;
      dma_start_2d <= 0;
      dma_start_3d <= 0;
      dma_start_4d <= 0;
      dma_last_1d <= 0;
      dma_last_2d <= 0;
      dma_last_3d <= 0;
      dma_last_4d <= 0;
      dma_last_5d <= 0;
      block_word_1d <= 0;
      block_word_2d <= 0;
      block_length_1d <= 0;
      block_length_2d <= 0;
      span_addr <= 0;
      span_count <= 0;
      dma_count <= 0;
      v_current_safe <= 0;
      test_addr <= 0;
      staged_data <= 0;
      span_length <= 0;
      end
   else
      begin
      horizontal_flag_4d <= horizontal_flag_3d;
      refresh_strobe_0d <= horizontal_flag_3d && !horizontal_flag_4d;
      refresh_strobe_1d <= refresh_strobe_0d;
      refresh_strobe_2d <= refresh_strobe_1d;
      refresh_strobe_3d <= refresh_strobe_2d;
      refresh_strobe_4d <= refresh_strobe_3d;
      refresh_strobe_5d <= refresh_strobe_4d;
      refresh_strobe    <= refresh_strobe_5d;
      dma_grant_1d <= dma_grant;
      block_grant <= (dma_grant || dma_grant_1d) && (!split || split_last);
      if (dma_grant)
         begin
         granted <= 1;
         end
      else
         begin
         if (dma_start)
            begin
            granted <= 0;
            end
         end
      dma_start_1d <= dma_start && granted;
      dma_start_2d <= dma_start_1d;
      dma_start_3d <= dma_start_2d;
      dma_start_4d <= dma_start_3d;
      dma_last_1d <= dma_last;
      dma_last_2d <= dma_last_1d;
      dma_last_3d <= dma_last_2d;
      dma_last_4d <= dma_last_3d;
      dma_last_5d <= dma_last_4d;
      case (state)
         STATE_IDLE :
            begin
            if (block_start_3d && !block_start_4e)
               begin
               block_start_4e <= 1;
               block_partial <= 0;
               span_count <= block_count;
               state <= STATE_READ_REQ;
               end
            else
               begin
               block_start_4e <= block_start_4e && block_start_3d;
               end
            end
         STATE_READ_REQ :
            begin
            block_start_4e <= block_start_4e && block_start_3d;
            if (dma_grant || granted)
               begin
               state <= STATE_READ_WAIT;
               end
            end
         STATE_READ_WAIT :
            begin
            block_start_4e <= block_start_4e && block_start_3d;
            if (dma_start_4d)
               begin
               if (!bank_sel)
                  begin
                  pre_wen_a <= !ctrl[11];
                  end
               else
                  begin
                  pre_wen_b <= !ctrl[11];
                  end
               span_addr <= block_word_2d;
               span_length <= block_length_2d;
               state <= STATE_READ;
               end
            end
         STATE_READ :
            begin
            block_start_4e <= block_start_4e && block_start_3d;
            span_addr <= span_addr + 1;
            span_length <= span_length - 1;
            if (partial)
               begin
               block_partial <= 1;
               end
            if (dma_last_5d)
               begin
               pre_wen_a <= 0;
               pre_wen_b <= 0;
               if (span_length != 0)
                  begin
                  state <= STATE_READ_WAIT;
                  end
               else
                  begin
                  if (span_count != 0)
                     begin
                     span_count <= span_count - 1;
                     state <= STATE_READ_WAIT;
                     end
                  else
                     begin
                     state <= STATE_IDLE;
                     end
                  end
               end
            end
      endcase
      if (dma_grant)
         begin
         block_word_1d <= block_word + dma_address[6:3] - block_address[6:3];
         block_length_1d <= split_last ? (block_end[6:3]  - split_addr[6:3]) :
					 block_length[6:3];
         block_start_4d <= block_start_4d && block_start_3d;
         if (!split || split_last)
            begin
            if (dma_count != 0)
               begin
               dma_count <= dma_count - 1;
               end
            else
               begin
               dma_request <= 0;
               end
            end
         end
      else
         begin
         if (block_start_3d && !block_start_4d)
            begin
            block_start_4d <= 1;
            dma_request <= 1;
            dma_count <= block_count;
            end
         else
            begin
            block_start_4d <= block_start_4d && block_start_3d;
            end
         end
      if (dma_grant_1d)
         begin
         if (split)
            begin
            split_last <= !split_last;
            end
         else
            begin
            split_last <= 0;
            end
         end
      if (dma_start)
         begin
         block_word_2d <= block_word_1d;
         block_length_2d <= block_length_1d;
         end
      if (refresh_strobe)
         begin
         v_current_safe <= v_current;
         end
      if (reg_write_enable && (reg_address == 4))
         begin
	 vi_int <= 0;
         end
      else
         begin
         pre_int_4d <= pre_int_3d;
         if (pre_int_3d && !pre_int_4d)
            begin
            vi_int <= 1;
            end
         end
      if (reg_write_enable)
         begin
         case (reg_address)
            0 : begin
		ctrl[15:0] <= reg_write_data[15:0];
                end
            1 : begin
		origin[23:0] <= reg_write_data[23:0];
              	end
            2 : begin
		width[11:0] <= reg_write_data[11:0];
               	end
            3 : begin
		v_int[9:0] <= reg_write_data[9:0];
               	end
            4 : begin
		end
	    5 : begin
		burst_start[9:0] <= reg_write_data[29:20];
		vsync_width[3:0] <= reg_write_data[19:16];
		burst_width[7:0] <= reg_write_data[15:8];
		hsync_width[7:0] <= reg_write_data[7:0];
		end
	    6 : begin
		v_sync_period[9:0] <= reg_write_data[9:0];
		end
	    7 : begin
		h_sync_period[11:0] <= reg_write_data[11:0];
		leap_pattern[4:0] <= reg_write_data[20:16];
		end
	    8 : begin
		hsync_leap_b[11:0] <= reg_write_data[11:0];
		hsync_leap_a[11:0] <= reg_write_data[27:16];
		end
	    9 : begin
		h_video_end[9:0] <= reg_write_data[9:0];
		h_video_start[9:0] <= reg_write_data[25:16];
		end
	   10 : begin
		v_video_end[9:0] <= reg_write_data[9:0];
		v_video_start[9:0] <= reg_write_data[25:16];
		end
	   11 : begin
		v_burst_end[9:0] <= reg_write_data[9:0];
		v_burst_start[9:0] <= reg_write_data[25:16];
		end
	   12 : begin
		x_scale[11:0] <= reg_write_data[11:0];
		x_offset[11:0] <= reg_write_data[27:16];
		end
	   13 : begin
		y_scale[11:0] <= reg_write_data[11:0];
		y_offset[11:0] <= reg_write_data[27:16];
		end
	   14:	begin
		test_addr <= reg_write_data[6:0];
		end
	   15 : begin
		case (test_addr[1:0])
		0:	begin
			{staged_data[ 71: 56],
			 staged_data[ 53: 38]} <=
				reg_write_data;
			end
		1:	begin
			{staged_data[ 35: 20],
			 staged_data[ 17:  2]} <=
				reg_write_data;
			end
		2:	begin
			{staged_data[ 55: 54],
			 staged_data[ 37: 36],
			 staged_data[ 19: 18],
			 staged_data[  1:  0]} <=
				reg_write_data[7:0];
			end
		endcase
		end
         endcase
         end
      end
   end

// register read mux
assign reg_read_data =
	reg_address[3] ?
		(reg_address[2] ?
			(reg_address[1] ?
				(reg_address[0] ?
					test_data :
					test_addr) :
				(reg_address[0] ?
					{y_offset[11:0],4'b0,
					 y_scale} :
					{x_offset[11:0],4'b0,
					 x_scale[11:0]})) :
			(reg_address[1] ?
				(reg_address[0] ?
					{v_burst_start[9:0],6'b0,
					 v_burst_end[9:0]} :
					{v_video_start[9:0],6'b0,
					 v_video_end[9:0]}) :
				(reg_address[0] ?
					{h_video_start[9:0],6'b0,
					 h_video_end[9:0]} :
					{hsync_leap_a[11:0],4'b0,
					 hsync_leap_b[11:0]}))) :
		(reg_address[2] ?
			(reg_address[1] ?
				(reg_address[0] ?
					{leap_pattern[4:0],4'b0,
					h_sync_period[11:0]} :
					v_sync_period) :
				(reg_address[0] ?
					{burst_start[9:0],
					 vsync_width[3:0],
					 burst_width[7:0],
					 hsync_width[7:0]} :
					v_current_safe)) :
			(reg_address[1] ?
				(reg_address[0] ?
					v_int :
					width) :
				(reg_address[0] ?
					origin :
					ctrl)));

assign vbus_clock_enable_l = ~ctrl[5];

endmodule // vi_controller.v