vi_sync_fsm.ss
3.73 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = vi_sync_fsm
wire_load = 256000
standard_load = 0.01
clock = vclk
default_input_delay = 1.5
default_output_delay = 14.0
default_input_load = 10
default_output_load = 20
default_drive_cell = dfntnh
default_drive_pin = q
default_period = 16.0
default_max_transition = 1.5
default_uncertainty = 0.5
hdlin_force_use_ffgen = false
/*****************************************************************************/
/* set the path and read */
/*****************************************************************************/
search_path = search_path + "../src" + "../../syn"
synthetic_library = synthetic_library + dw02.sldb
link_library = link_library + dw02.sldb
read -f verilog ../src/vi_sync_fsm.v
current_design = module
/*****************************************************************************/
/* default environment */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/*****************************************************************************/
/* clock and reset constraints */
/*****************************************************************************/
create_clock clock -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -propagated -uncertainty default_uncertainty clock
set_dont_touch_network clock
/*****************************************************************************/
/* default constraint */
/*****************************************************************************/
set_max_area 0
set_dont_touch { ne35hd130d/nt01d* }
set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null
set_drive 0 { clock reset_l }
set_input_delay 8 -clock clock reset_l
set_max_transition default_max_transition current_design
/*****************************************************************************/
/* custom constraints */
/*****************************************************************************/
set_output_delay 10.0 -clock clock pixel_sync
/*****************************************************************************/
/* check */
/*****************************************************************************/
check_design > module + ".lint"
/*****************************************************************************/
/* compile */
/*****************************************************************************/
get_license Designware-Basic
compile -ungroup_all
/*****************************************************************************/
/* write */
/*****************************************************************************/
include "report.dc"
change_names -rules compass_rules -hierarchy
write -format edif -hierarchy -o module + ".edf" module
write -format db -hierarchy -o module + ".db" module
quit