div_rom.dprscr 221 Bytes Raw Blame History Permalink 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 #!/bin/csh -f # vlsishell << EOF cellcompiler load [tpl]nero2 div_rom edit 16 1024 div_rom.cod 3 false false vlsiModel optimized behavioral NECE35CC10 save output layout mcp pmd Transistor-Netlist exit exit EOF #
