carttst1.tdf
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TITLE "$Id: carttst1.tdf,v 1.1.1.1 2002/05/17 06:07:56 blythe Exp $ Copyright (C) 1994, 1995 Silicon Graphics, Inc.";
%*************************************************************************%
%* *%
%* Copyright (C) 1994, 1995 Silicon Graphics, Inc. *%
%* *%
%* These coded instructions, statements, and computer programs contain *%
%* unpublished proprietary information of Silicon Graphics, Inc., and *%
%* are protected by Federal copyright law. They may not be disclosed *%
%* to third parties or copied or duplicated in any form, in whole or *%
%* in part, without the prior written consent of Silicon Graphics, Inc. *%
%* *%
%*************************************************************************%
% cycle counts for various cycle types (1 less than actual) %
constant CNT_ADR = 5;
constant CNT_PGBRK = 1;
constant CNT_LWAIT = 9;
constant CNT_RD_WR = 9;
constant CNT_RELWIDTH = 3;
constant CNT_IDLE = 9;
subdesign carttst1
(
clk, RstB, cmd[3..0] : INPUT;
aleh, alel, rdB, wrB, chk : OUTPUT;
ad[15..0] : BIDIR;
)
variable
clock, adr_out[31..0], pagebreak, hold_idle, top_adr : NODE;
cycleend, pbreak, adrinc, dataoe, count[7..0], nextcnt[7..0],
cntzero, prechk[7..0], chk : DFF;
ad_int[15..0], adr[23..1], pgcnt[3..0], r_w, invert,
aleh, alel, wrB, rdB : DFFE;
ad[15..0] : TRI;
begin
clock = global(clk);
adr_out[31..24] = 0;
adr_out[23..1] = adr[];
adr_out[0] = GND;
pagebreak = (adr_out[6..0] == H"7e");
hold_idle = !cmd[0];
if (cmd[1]) then top_adr = (adr_out[22..0] == H"7ffffe");
else top_adr = (adr_out[23..0] == H"fffffe");
end if;
pbreak.clk = clock;
pbreak = (adrinc & pagebreak) # (pbreak & !aleh);
cycleend.clk = clock;
cycleend = (adrinc & pagebreak & (pgcnt[] == 15)) # (cycleend & !aleh);
chk.clk = clock;
chk = (prechk[] != 0);
prechk[].clk = clock;
prechk[0] = cntzero & !rdB & (ad[1..0] != ad_int[1..0]);
prechk[1] = cntzero & !rdB & (ad[3..2] != ad_int[3..2]);
prechk[2] = cntzero & !rdB & (ad[5..4] != ad_int[5..4]);
prechk[3] = cntzero & !rdB & (ad[7..6] != ad_int[7..6]);
prechk[4] = cntzero & !rdB & (ad[9..8] != ad_int[9..8]);
prechk[5] = cntzero & !rdB & (ad[11..10] != ad_int[11..10]);
prechk[6] = cntzero & !rdB & (ad[13..12] != ad_int[13..12]);
prechk[7] = cntzero & !rdB & (ad[15..14] != ad_int[15..14]);
r_w.clk = clock;
r_w.clrn = rstB;
r_w.ena = adrinc & top_adr;
r_w = !r_w;
invert.clk = clock;
invert.clrn = rstB;
invert.ena = adrinc & top_adr & r_w;
invert = !invert;
aleh.clk = clock;
aleh.prn = rstB;
aleh.ena = cntzero;
!aleh = alel # (!aleh & !pbreak);
alel.clk = clock;
alel.clrn = rstB;
alel.ena = cntzero;
alel = aleh & (!hold_idle # alel);
rdB.clk = clock;
rdB.prn = rstB;
rdB.ena = cntzero;
!rdB = !alel & !aleh & rdB & r_w & !pbreak;
wrB.clk = clock;
wrB.prn = rstB;
wrB.ena = cntzero;
!wrB = !alel & !aleh & wrB & !r_w & !pbreak;
% downcounter to provide delays for each state %
count[].clk = clock;
count[].prn = rstB;
if (!cntzero) then count[] = count[] - 1;
elsif (aleh & !alel & hold_idle) then count[] = 0;
else count[] = nextcnt[];
end if;
nextcnt[].clk = clock;
if (aleh) then nextcnt[] = CNT_ADR;
elsif (!aleh & alel) then nextcnt[] = CNT_LWAIT;
elsif (cycleend) then nextcnt[] = CNT_IDLE;
elsif (pbreak) then nextcnt[] = CNT_PGBRK;
elsif (rdB & wrB) then nextcnt[] = CNT_RD_WR;
else nextcnt[] = CNT_RELWIDTH;
end if;
% select for count == 0 %
cntzero.clk = clock;
cntzero = ((count[] == 0) & hold_idle & aleh & !alel) # (count[] == 1);
pgcnt[].clk = clock;
pgcnt[].clrn = rstB;
pgcnt[].ena = adrinc & pagebreak;
pgcnt[] = pgcnt[] + 1;
adrinc.clk = clock;
adrinc = (count[] == 1) & (!rdB # !wrB);
adr[].clk = clock;
adr[].clrn = rstB;
adr[].ena = adrinc;
if (!cmd[1]) then adr[] = adr[] + 1;
else adr[23] = gnd;
adr[22..1] = adr[22..1] + 1;
end if;
dataoe.clk = clock;
dataoe = alel # !wrB;
ad[].oe = dataoe;
ad[] = ad_int[];
ad_int[].clk = clock;
if (aleh) then ad_int[] = adr_out[31..16];
elsif (!aleh & alel) then ad_int[] = adr_out[15..0];
elsif (invert) then ad_int[] = !adr_out[16..1];
else ad_int[] = adr_out[16..1];
end if;
end;