// Verilog netlist of
//"/home/merc/usr8/w5/rev1.0/chip/GUIRAC/w5RAC"

// HDL models

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/GUIRAC/w5CCAnal/w5CCAnal.v"
module w5CCAnal (up, op5, op4, op3, op2, op1, op0, sub, add, CCtlPgm, VBias, Vref, ictrlOn, slowClk, scanM_B);
output          up;
input           op5, op4, op3, op2, op1, op0;
input           sub, add, CCtlPgm, VBias, Vref, ictrlOn, slowClk, scanM_B;
 
reg     [6:0]   Tval;   // Target value to be reached
reg     [6:0]   Cval;   // current value 
reg             up;
 
wire    Okay = CCtlPgm & VBias & ictrlOn & Vref & scanM_B;
 
// Timming waveform for this blocks:
//
//            -------           -------------
//    slowclk        \         /
//                    --------- 
//                     -------------- 
//    ictrlOn         /              \
//            --------                -------
//            ----------- -------------------
//    up                 X
//            ----------- -------------------
//
// John Ho 8/31/93
//
//
//initial begin up = 0; #1; up =0; #1; up =0; end
// take the effect of sub and add to get the seven bit current value
always @(posedge slowClk)
    begin
        Cval[6:1]       = {op5,op4,op3,op2,op1,op0};
        Cval[0]         = 0;
        if ((Cval > 0) && (Cval < 7'b1111111))
        begin
          if (sub == 1) Cval = Cval - 1;
          else if (add == 1) Cval = Cval + 1;
        end
        #1;
        if (Tval > Cval) up = Okay;
        else up = !Okay;
//        $display($time,,"CV:%h, TV:%h, up:%b, add:%b, sub:%b, ion:%b",
//                         Cval,Tval,up,add,sub,ictrlOn);
    end
 
endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/schema/capN/capN.v"
module capN (PLUS, MINUS);
    inout PLUS;
    inout MINUS;
endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/schema/vqmsry/msrY.v"
// This cell is identical to msr (circuit wise)
// The reason for making it a special cell is:
//  -  We need to generate SynClk with zero delay from rc for
//     all the closks to line up.
module msrY (Q, D, clk, clk_);
output Q;
input D, clk, clk_;

latWX U7(Q, hnl_2, clk, clk_);
latW U4(hnl_2, hnl_6);
tranif1 U2(D, hnl_6, clk_);
tranif0 U3(D, hnl_6, clk);

endmodule

module latWX (Y, A, clk, clk_);
output Y;
input  A, clk, clk_;
reg    Yr;

always @ (posedge clk) Yr = A;
assign Y  = (Yr ^ (clk ^ clk_));
endmodule


// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/DLL/w5DLL/w5DLL.v"
module w5DLL (tclkDrv_, rclkDrv_, tclkBus, rclkBus,
              ByPass, TxCLK, RxCLK, Vref, PwrUp, tclkpll, rclkpll);

output	tclkDrv_, rclkDrv_, tclkBus, rclkBus;
input	ByPass, TxCLK, RxCLK, Vref, PwrUp, tclkpll, rclkpll;

integer xr, xt, yr, yt;
reg     sc, tc, Okay, scr, tcr;
event   St_rclk, St_tclk;
 
initial
begin
        sc = 0;
        tc = 0;
        xr = 0;
        xt = 0;
        yr = 0;
        yt = 0;
        Okay = 0;
        #1280;
        Okay = 1;
end
 
always @(posedge PwrUp)
	begin
	Okay = 0;
	#1280;
	Okay = 1;
	end

initial @(negedge RxCLK)
         begin
          yr = $stime;
          @(negedge RxCLK)
           ->St_rclk;
         end
 
initial @(negedge TxCLK)
         begin
          yt = $stime;
          @(negedge RxCLK)
           ->St_tclk;
         end
 
always @(St_rclk)
        while (1)
         begin
          xr = yr;
          yr = $stime;
          sc = 0;
          sc = # ((yr-xr)/2) 1;
          @(negedge RxCLK);
         end
 
always @(St_tclk)
        while (1)
         begin
          xt = yt;
          yt = $stime;
          `ifdef RSIMCLK
            // reduce offset between tclk and rclk for rsim
            tc <= # (((yt-xt)/4) - 9) 1;
            tc <= # ((3*(yt-xt)/4) - 9) 0;
          `else
            // normal offset between tclk and rclk for verilog
            tc <= # (((yt-xt)/4) - 0) 1;
            tc <= # ((3*(yt-xt)/4) - 0) 0;
          `endif
          @(negedge TxCLK);
         end

assign	rclkDrv_ = (Okay == 1) ? (!sc & Vref & PwrUp & !ByPass) : ('bx);
assign	tclkDrv_ = (Okay == 1) ? (!tc & Vref & PwrUp & !ByPass) : ('bx);

assign  rclkBus =  RxCLK & ByPass;
not     #10 i0(tclkBus,rclkBus);

endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/GUIRAC/w5ISBiGn/w5ISBiGn.v"
module w5ISBiGn (VBias, pd);
    output VBias;
    input  pd;

assign VBias = !pd;

endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/GUIRAC/w5ISamp/w5ISamp.v"
module w5ISamp (Q, Q_, D, CLK, VBias, Vref);
    output Q;
    output Q_;
    input D;
    input CLK;
    input VBias;
    input Vref;

    reg		x,y; 

always @(posedge CLK) x=D;
always @(negedge CLK) y=x;
 
nand #10 i0(Q, y, Vref, VBias);
assign Q_ = ~Q;

endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/schema/resistPS/resistPS.v"
module resistPS (PLUS, MINUS);
 inout PLUS, MINUS;
 rtran N1(PLUS, MINUS);
endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/schema/vqmsrsx/msrsX.v"
// This cell is identical to msrs (circuit wise)
// The reasons for making it a special cell are:
// (1) It needs to be initialized. The initialization
//     is needed because verilog initializes it to X.
//     This cell is used in counters, where the initial count is
//     irrelevant but it needs to be some value and not "X's"
//     Examples: vqPrsclr, vqCCFsm
module msrsX (Q, D, clk, clk_, se, se_, si);
output Q;
input D, clk, clk_, se, se_, si;

latW U4(hnl_2, hnl_3);
latWY U7(Q, hnl_2, clk);
cxfr U21(hnl_4, se, se_, si);
cxfr U14(hnl_4, se_, se, D);
cxfr U2(hnl_3, clk_, clk, hnl_4);
endmodule

module latWY (Y, A, clk);
output Y;
input  A, clk;
reg    Yr;

always @ (posedge clk) Yr = #1 !A;
assign Y  = Yr;
endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/schema/vqcxfr/cxfr.v"
module cxfr (D, GN, GP, S);
 output D;
 input  S;
 input GN, GP;
 wire T;
 assign T = GP ^ (1'bx || (GN ^ GP));
 nmos N1(D, S, T);
endmodule

// HDL file - 
// /home/merc/usr8/w5/rev1.0/chip/schema/vqlatw/latW.v"
module latW (Y, A);
output Y;
inout A;

not #1                i0(Y, A);
not    (weak1, weak0) i1(A, Y);

endmodule



// End HDL models


module w5zerboB (Q, Qb, D);
output Q, Qb;
input D;
supply1 vddA;
supply1 vddR;
supply0 gndR;
not #(0) U4(outc, outb);
not #(0) U2(Q, outa);
not #(0) U1(outa, D);
not #(0) U5(Qb, outc);
not #(0) U3(outb, D);
endmodule

module vqmxlat (Q_, D, clk, clk_, se, se_, si);
output Q_;
input D, clk, clk_, se, se_, si;
supply1 vddA;
supply1 vddR;
supply0 gndR;
latW U8(Q_, hnl_0);
cxfr U1(sh, se_, se, D);
cxfr U11(sh, se, se_, si);
cxfr U6(hnl_0, clk, clk_, sh);
endmodule

module vqlatch (Q_, D, clk, clk_);
output Q_;
input D, clk, clk_;
supply1 vddA;
supply1 vddR;
supply0 gndR;
cxfr U5(hnl_1, clk, clk_, D);
latW U6(Q_, hnl_1);
endmodule

module w5OsftX (soE_, soO_, tdE, tdO, clk, clk_, dE, dO, scanM_, se, se_, siE, siO);
output soE_, soO_, tdE, tdO;
input clk, clk_, dE, dO, scanM_, se, se_, siE, siO;
supply1 vddA;
supply1 vddR;
supply0 gndR;
vqmxlat I4(tdE, dE, clk_, clk, se, se_, siE);
vqmxlat I11(hnl_2, dO, clk_, clk, se, se_, siO);
vqlatch I1(tdO, hnl_3, clk, clk_);
vqlatch I12(soE_, hnl_4, clk, clk_);
not #(0) U2(hnl_3, hnl_2);
not #(0) U13(hnl_5, scanM_);
not #(0) U3(hnl_4, hnl_6);
cxfr U9(hnl_6, hnl_5, scanM_, tdE);
cxfr U7(soO_, hnl_5, scanM_, tdO);
tranif1 N15(hnl_6, gndR, scanM_);
tranif1 N14(soO_, gndR, scanM_);
endmodule

module vqmx02 (out, a, b, sa, sb);
output out;
input a, b, sa, sb;
supply1 vddA;
supply1 vddR;
supply0 gndR;
not #(0) U3(out, hnl_7);
cxfr U2(hnl_7, sb, sa, b);
cxfr U1(hnl_7, sa, sb, a);
endmodule

module vqmsrs (Q, D, clk, clk_, se, se_, si);
output Q;
input D, clk, clk_, se, se_, si;
supply1 vddA;
supply1 vddR;
supply0 gndR;
latW U4(hnl_8, hnl_9);
latW U7(Q, hnl_1);
cxfr U21(sh, se, se_, si);
cxfr U14(sh, se_, se, D);
cxfr U2(hnl_9, clk_, clk, sh);
cxfr U5(hnl_1, clk, clk_, hnl_8);
endmodule

module w5OShift (soE_, tdE, tdO, Btd_7_, Btd_6_, Btd_5_, Btd_4_, Btd_3_, Btd_2_, Btd_1_, Btd_0_, bist, loadL, loadL_, scanM_, se, siO_, tclkL, tclkL_, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_,
td_0_);
output soE_, tdE, tdO;
input Btd_7_, Btd_6_, Btd_5_, Btd_4_, Btd_3_, Btd_2_, Btd_1_, Btd_0_, bist, loadL, loadL_, scanM_, se, siO_, tclkL, tclkL_, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_, td_0_;
supply1 vddA;
supply1 vddR;
supply0 gndR;
w5OsftX I131(soE_, hnl_10, tdE, tdO, tclkL_, tclkL, s0, s1, scanM_, loadL_, loadL, hnl_11, hnl_12);
not #(0) U111(hnl_13, bist);
nand #(0) U69(hnl_14, se, hnl_10);
nand #(0) U70(hnl_15, se, siO_);
vqmx02 T0(s0, Btd_0_, td_0_, bist, hnl_13);
vqmx02 T1(s1, Btd_1_, td_1_, bist, hnl_13);
vqmx02 T3(s3, Btd_3_, td_3_, bist, hnl_13);
vqmx02 T5(s5, Btd_5_, td_5_, bist, hnl_13);
vqmx02 T7(s7, Btd_7_, td_7_, bist, hnl_13);
vqmx02 T6(s6, Btd_6_, td_6_, bist, hnl_13);
vqmx02 T4(s4, Btd_4_, td_4_, bist, hnl_13);
vqmx02 T2(s2, Btd_2_, td_2_, bist, hnl_13);
vqmsrs E2(hnl_11, s2, tclkL_, tclkL, loadL_, loadL, hnl_16);
vqmsrs O3(hnl_17, s5, tclkL_, tclkL, loadL_, loadL, hnl_18);
vqmsrs O4(hnl_18, s7, tclkL_, tclkL, loadL_, loadL, hnl_15);
vqmsrs E4(hnl_19, s6, tclkL_, tclkL, loadL_, loadL, hnl_14);
vqmsrs E3(hnl_16, s4, tclkL_, tclkL, loadL_, loadL, hnl_19);
vqmsrs O2(hnl_12, s3, tclkL_, tclkL, loadL_, loadL, hnl_17);
endmodule

module vqmxfr (out, a, b, sa, sb);
output out;
input a, b, sa, sb;
supply1 vddA;
supply1 vddR;
supply0 gndR;
cxfr U1(out, sa, sb, a);
cxfr U2(out, sb, sa, b);
endmodule

module vqmsr (Q, D, clk, clk_);
output Q;
input D, clk, clk_;
supply1 vddA;
supply1 vddR;
supply0 gndR;
latW U8(hnl_20, hnl_21);
latW U10(Q, hnl_0);
cxfr U7(hnl_21, clk_, clk, D);
cxfr U6(hnl_0, clk, clk_, hnl_20);
endmodule

module w5IShift (even, odd, rd_7_, rd_6_, rd_5_, rd_4_, rd_3_, rd_2_, rd_1_, rd_0_, soE, soO, rEnL, rEnL_, rclkL, rclkL_, rdE, rdO_, scanM_, se, siE, siO);
output even, odd, rd_7_, rd_6_, rd_5_, rd_4_, rd_3_, rd_2_, rd_1_, rd_0_, soE, soO;
input rEnL, rEnL_, rclkL, rclkL_, rdE, rdO_, scanM_, se, siE, siO;
supply1 vddA;
supply1 vddR;
supply0 gndR;
msrsX E1(even, rdE, rclkL, rclkL_, se, hnl_22, siE);
vqmxfr I493(odd, siO, hnl_23, hnl_24, scanM_);
vqmsr O4(soO, r3, rclkL, rclkL_);
vqmsr O2(r5, odd, rclkL, rclkL_);
vqmsr O3(r3, r5, rclkL, rclkL_);
vqmsr E2(r4, even, rclkL, rclkL_);
vqmsr E3(r2, r4, rclkL, rclkL_);
vqmsr E4(soE, r2, rclkL, rclkL_);
vqlatch O1(hnl_23, rdO_, rclkL, rclkL_);
vqlatch R0(hnl_25, soE, rEnL, rEnL_);
vqlatch R1(hnl_26, soO, rEnL, rEnL_);
vqlatch R2(hnl_27, r2, rEnL, rEnL_);
vqlatch R3(hnl_28, r3, rEnL, rEnL_);
vqlatch R4(hnl_29, r4, rEnL, rEnL_);
vqlatch R5(hnl_30, r5, rEnL, rEnL_);
vqlatch R6(hnl_31, even, rEnL, rEnL_);
vqlatch R7(hnl_32, odd, rEnL, rEnL_);
not #(0) U497(hnl_24, scanM_);
not #(0) U266(hnl_22, se);
not #(0) U267(rd_7_, hnl_32);
not #(0) U394(rd_6_, hnl_31);
not #(0) U395(rd_5_, hnl_30);
not #(0) U396(rd_4_, hnl_29);
not #(0) U397(rd_3_, hnl_28);
not #(0) U398(rd_2_, hnl_27);
not #(0) U399(rd_1_, hnl_26);
not #(0) U400(rd_0_, hnl_25);
endmodule

module w5Opad (Vrefi, data, pad, Vref, op_5_, op_4_, op_3_, op_2_, op_1_, op_0_);
output Vrefi, data, pad;
input Vref, op_5_, op_4_, op_3_, op_2_, op_1_, op_0_;
supply1 vddA;
supply1 vddR;
supply0 gndR;
tranif0 P34(pad, vddR, vddR);
resistPS R24(pad, data);
resistPS R22(Vref, Vrefi);
tranif1 N33(pad, gndR, op_5_);
tranif1 N32(pad, gndR, op_1_);
tranif1 N29(pad, gndR, op_4_);
tranif1 N21(pad, gndR, op_3_);
tranif1 N20(pad, gndR, op_0_);
tranif1 N19(pad, gndR, op_2_);
endmodule

module w5Omux (op_5_, op_4_, op_3_, op_2_, op_1_, op_0_, evenData, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, oddData, tclkL, tclkL_b);
output op_5_, op_4_, op_3_, op_2_, op_1_, op_0_;
input evenData, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, oddData, tclkL, tclkL_b;
supply1 vddA;
supply1 vddR;
supply0 gndR;
not #(0) U112(op_2_, i2);
not #(0) U113(op_3_, i3);
not #(0) U115(op_4_, i4);
not #(0) U114(op_5_, i5);
not #(0) U111(op_1_, i1);
not #(0) U82(op_0_, i0);
nand #(1) U123(hnl_33, oddData, ictrl_4_);
nand #(1) U124(hnl_34, evenData, ictrl_4_);
nand #(1) U121(hnl_35, oddData, ictrl_3_);
nand #(1) U122(hnl_36, evenData, ictrl_3_);
nand #(1) U119(hnl_37, oddData, ictrl_2_);
nand #(1) U120(hnl_38, evenData, ictrl_2_);
nand #(1) U118(hnl_39, oddData, ictrl_1_);
nand #(1) U117(hnl_40, evenData, ictrl_1_);
nand #(1) U116(hnl_41, oddData, ictrl_0_);
nand #(1) U60(hnl_42, evenData, ictrl_0_);
nand #(1) U125(hnl_43, evenData, ictrl_5_);
nand #(1) U126(hnl_44, oddData, ictrl_5_);
cxfr U76(i5, tclkL, tclkL_b, hnl_44);
cxfr U66(i5, tclkL_b, tclkL, hnl_43);
cxfr U52(i4, tclkL, tclkL_b, hnl_33);
cxfr U99(i4, tclkL_b, tclkL, hnl_34);
cxfr U56(i3, tclkL, tclkL_b, hnl_35);
cxfr U71(i3, tclkL_b, tclkL, hnl_36);
cxfr U53(i2, tclkL, tclkL_b, hnl_37);
cxfr U79(i2, tclkL_b, tclkL, hnl_38);
cxfr U75(i1, tclkL, tclkL_b, hnl_39);
cxfr U87(i1, tclkL_b, tclkL, hnl_40);
cxfr U81(i0, tclkL, tclkL_b, hnl_41);
cxfr U62(i0, tclkL_b, tclkL, hnl_42);
endmodule

module w5IObuf (rdE, rdO_, pad, Vref, evenData, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, oddData, pd, rclkL, rclkL_, scanM_, tclkL, tclkL_);
output rdE, rdO_;
inout pad;
input Vref, evenData, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, oddData, pd, rclkL, rclkL_, scanM_, tclkL, tclkL_;
supply1 vddA;
supply1 vddR;
supply0 gndR;
w5Opad OP(hnl_45, hnl_46, pad, Vref, op_5_, op_4_, op_3_, op_2_, op_1_, op_0_);
w5Omux OM(op_5_, op_4_, op_3_, op_2_, op_1_, op_0_, evenData, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, oddData, tclkL, tclkL_);
w5ISamp ISO(hnl_47, hnl_48, hnl_46, rclkL, vbias, hnl_45);
w5ISamp ISE(hnl_49, hnl_50, hnl_46, rclkL_, vbias, hnl_45);
w5ISBiGn I136(vbias, pd);
nand #(1) U141(rdO_, hnl_47, scanM_);
nand #(1) U139(rdE, hnl_50, scanM_);
endmodule

module ppoint ();
supply1 vddA;
supply1 vddR;
supply0 gndR;
endmodule

module w5IOcell (rd_7_, rd_6_, rd_5_, rd_4_, rd_3_, rd_2_, rd_1_, rd_0_, soIE, soIO, soOE_, pad, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadL, loadL_, pd, rEnL,
rEnL_, rclk, scanM_, se, siIE, siIO, siOO_, srd_1_, srd_0_, tclk, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_, td_0_);
output rd_7_, rd_6_, rd_5_, rd_4_, rd_3_, rd_2_, rd_1_, rd_0_, soIE, soIO, soOE_;
inout pad;
input Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadL, loadL_, pd, rEnL, rEnL_, rclk, scanM_, se, siIE, siIO, siOO_, srd_1_, srd_0_, tclk, td_7_, td_6_, td_5_, td_4_,
td_3_, td_2_, td_1_, td_0_;
supply1 vddA;
supply1 vddR;
supply0 gndR;
w5zerboB ZBT(tclkL, tclkL_, tclk);
w5zerboB ZBR(rclkL, rclkL_, rclk);
w5OShift OS(soOE_, tdE, tdO, srd_1_, srd_0_, rd_7_, rd_6_, rd_5_, rd_4_, rd_3_, rd_2_, bist, loadL, loadL_, scanM_, se, siOO_, tclkL, tclkL_, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_, td_0_);
w5IShift IS(hnl_51, hnl_52, rd_7_, rd_6_, rd_5_, rd_4_, rd_3_, rd_2_, rd_1_, rd_0_, soIE, soIO, rEnL, rEnL_, rclkL, rclkL_, rdE, rdO_, scanM_, se, siIE, siIO);
w5IObuf IOB(rdE, rdO_, pad, Vref, tdE, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, tdO, pd, rclkL, rclkL_, scanM_, tclkL, tclkL_);
ppoint I97();
ppoint I96();
ppoint I95();
ppoint I94();
ppoint I93();
ppoint I92();
ppoint I91();
ppoint I90();
ppoint I89();
ppoint I88();
endmodule

module vqmsrsz (Q_, D, clk, clk_, se, se_, si);
output Q_;
input D, clk, clk_, se, se_, si;
supply1 vddA;
supply1 vddR;
supply0 gndR;
cxfr U26(hnl_53, clk_, clk, hnl_54);
cxfr U27(hnl_54, se, se_, si);
cxfr U28(hnl_54, se_, se, D);
cxfr U25(Q_, clk, clk_, hnl_55);
latW U24(hnl_56, Q_);
latW U23(hnl_55, hnl_53);
endmodule

module vqmsrsy (Q, Q_, D, clk, clk_, se, se_, si);
output Q, Q_;
input D, clk, clk_, se, se_, si;
supply1 vddA;
supply1 vddR;
supply0 gndR;
not #(0) U34(hnl_57, hnl_58);
latW U32(Q_, hnl_59);
latW U29(Q, hnl_53);
latW U28(hnl_58, hnl_54);
cxfr U33(hnl_59, clk, clk_, hnl_57);
cxfr U31(sh, se_, se, D);
cxfr U30(sh, se, se_, si);
cxfr U27(hnl_54, clk_, clk, sh);
cxfr U26(hnl_53, clk, clk_, hnl_58);
endmodule

module w5IOCtlB (loadBE, loadBE_, loadL1, loadL1_, loadL2, loadL2_, rEnL1, rEnL1_, rEnL2, rEnL2_, so, ExtBE, ldBD, ldBE, rEn, scanM_, sclkL, sclkL_, se, si, tclkL, tclkL_);
output loadBE, loadBE_, loadL1, loadL1_, loadL2, loadL2_, rEnL1, rEnL1_, rEnL2, rEnL2_, so;
input ExtBE, ldBD, ldBE, rEn, scanM_, sclkL, sclkL_, se, si, tclkL, tclkL_;
supply1 vddA;
supply1 vddR;
supply0 gndR;
ppoint I130();
ppoint I129();
ppoint I128();
ppoint I127();
nor #(0) U109(loadBE_, hnl_60, ExtBE);
nor #(0) U47(hnl_61, nldb1_, se);
nor #(0) U107(hnl_60, nlbb_, se);
nor #(0) U35(hnl_62, nldb2_, se);
nand #(0) U113(loadBE, hnl_41, hnl_38);
nand #(0) U116(hnl_41, nlbb, hnl_63);
nand #(0) U77(hnl_64, nldb1, hnl_63);
nand #(0) U27(hnl_65, nldb2, hnl_63);
vqmxlat I98(nrd1_, nrd_, sclkL_, sclkL, hnl_66, scanM_, gndR);
vqmxlat I96(nrd1, nrd, sclkL_, sclkL, hnl_66, scanM_, vddR);
vqmxlat I97(nrd2_, nrd_, sclkL_, sclkL, hnl_66, scanM_, gndR);
vqmxlat I95(nrd2, nrd, sclkL_, sclkL, hnl_66, scanM_, vddR);
vqmx02 I124(tclkd, vddR, gndR, tclkL_, tclkL);
vqmx02 I126(tclkd_, vddR, gndR, tclkL, tclkL_);
vqmx02 I85(xclk, vddR, gndR, vddR, gndR);
vqmx02 I88(xclk_, vddR, gndR, vddR, gndR);
vqmsrsz I55(nldb2, nlda2, tclkL_, tclkL, se, hnl_63, hnl_67);
vqmsrsz I72(nldb1, nlda1, tclkL_, tclkL, se, hnl_63, hnl_68);
vqmsrsz I10(nldb2_, nlda2_, tclkL_, tclkL, se, hnl_63, hnl_69);
vqmsrsz I28(nldb1_, nlda1_, tclkL_, tclkL, se, hnl_63, nld);
vqmsrsz I105(nlbb_, nlba_, tclkL_, tclkL, se, hnl_63, nlb);
vqmsrsz I111(nlbb, nlba, tclkL_, tclkL, se, hnl_63, hnl_70);
vqmsrsy I117(nlb, nlb_, ldBE, sclkL, sclkL_, se, hnl_63, hnl_71);
vqmsrsy I29(nrd, nrd_, rEn, sclkL, sclkL_, se, hnl_63, hnl_72);
vqmsrsy I42(nld, nld_, ldBD, sclkL, sclkL_, se, hnl_63, si);
vqlatch I91(nlda2, nld, tclkd_, tclkd);
vqlatch I114(nlba, nlb, tclkd_, tclkd);
vqlatch I94(nlda1, nld, tclkd_, tclkd);
vqlatch I110(nlba_, nlb_, tclkd_, tclkd);
vqlatch I92(nlda2_, nld_, tclkd_, tclkd);
vqlatch I93(nlda1_, nld_, tclkd_, tclkd);
not #(0) U71(loadL2_, hnl_62);
not #(0) U50(rEnL2, nrd2);
not #(0) U57(rEnL2_, nrd2_);
not #(0) U44(loadL2, hnl_65);
not #(0) U120(hnl_38, ExtBE);
not #(0) U49(so, hnl_73);
not #(0) U58(loadL1_, hnl_61);
not #(0) U23(rEnL1_, nrd1_);
not #(0) U75(rEnL1, nrd1);
not #(0) U3(loadL1, hnl_64);
not #(0) U108(hnl_70, nlbb_);
not #(0) U38(hnl_71, nldb2);
not #(0) U26(hnl_69, nldb1_);
not #(0) U115(hnl_72, nlbb);
not #(0) U31(hnl_68, nldb2_);
not #(0) U43(hnl_66, scanM_);
not #(0) U9(hnl_73, nrd);
not #(0) U16(hnl_67, nldb1);
not #(0) U19(hnl_63, se);
endmodule

module w5BEcell (pad, soOE_, ExtBE, Vref, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadL, loadL_, scanM_, se, siOO_, tclkL, tclkL_, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_,
td_0_);
output pad, soOE_;
input ExtBE, Vref, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadL, loadL_, scanM_, se, siOO_, tclkL, tclkL_, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_, td_0_;
supply1 vddA;
supply1 vddR;
supply0 gndR;
w5Opad OP(hnl_45, hnl_46, pad, Vref, op_5_, op_4_, op_3_, op_2_, op_1_, op_0_);
w5Omux OM(op_5_, op_4_, op_3_, op_2_, op_1_, op_0_, tdE, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, tdO, tclkL, tclkL_);
w5OShift OS(soOE_, tdE, tdO, gndR, gndR, gndR, gndR, gndR, gndR, vddR, vddR, ExtBE, loadL, loadL_, scanM_, se, siOO_, tclkL, tclkL_, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_, td_0_);
endmodule

module w5CtrlR (loadL1, loadL1_, loadL2, loadL2_, pad, rEnL1, rEnL1_, rEnL2, rEnL2_, so, soOE_, ExtBE, Vref, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, ldBD, ldBE, rEn, scanM_, sclk,
se, si, siOO_, tclk, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_, td_0_);
output loadL1, loadL1_, loadL2, loadL2_, pad, rEnL1, rEnL1_, rEnL2, rEnL2_, so, soOE_;
input ExtBE, Vref, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, ldBD, ldBE, rEn, scanM_, sclk, se, si, siOO_, tclk, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_, td_0_;
supply1 vddA;
supply1 vddR;
supply0 gndR;
w5zerboB BZT(tclkL, tclkL_, tclk);
w5zerboB BZS(sclkL, sclkL_, sclk);
w5IOCtlB IOCB(loadBE, loadBE_, loadL1, loadL1_, loadL2, loadL2_, rEnL1, rEnL1_, rEnL2, rEnL2_, so, ExtBE, ldBD, ldBE, rEn, scanM_, sclkL, sclkL_, se, si, tclkL, tclkL_);
w5BEcell BE(pad, soOE_, ExtBE, Vref, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, loadBE, loadBE_, scanM_, se, siOO_, tclkL, tclkL_, td_7_, td_6_, td_5_, td_4_, td_3_, td_2_, td_1_,
td_0_);
ppoint I60();
ppoint I59();
ppoint I58();
ppoint I57();
ppoint I56();
ppoint I55();
endmodule

module w5RACR (BusEnable, rfoo_71_, rfoo_70_, rfoo_69_, rfoo_68_, rfoo_67_, rfoo_66_, rfoo_65_, rfoo_64_, rfoo_63_, rfoo_62_, rfoo_61_, rfoo_60_, rfoo_59_, rfoo_58_, rfoo_57_, rfoo_56_, rfoo_55_,
rfoo_54_, rfoo_53_, rfoo_52_, rfoo_51_, rfoo_50_, rfoo_49_, rfoo_48_, rfoo_47_, rfoo_46_, rfoo_45_, rfoo_44_, rfoo_43_, rfoo_42_, rfoo_41_, rfoo_40_, soIE5, soOE5, srdo_1_, srdo_0_, BusData_8_,
BusData_7_, BusData_6_, BusData_5_, ExtBE, Vref, bist, etfoo_7_, etfoo_6_, etfoo_5_, etfoo_4_, etfoo_3_, etfoo_2_, etfoo_1_, etfoo_0_, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_,
ldBD, ldBE, pd, rEn, rclk, scanM_, sclk, se, siIO8, siOO8, srd_1_, srd_0_, tclk, tfoo_71_, tfoo_70_, tfoo_69_, tfoo_68_, tfoo_67_, tfoo_66_, tfoo_65_, tfoo_64_, tfoo_63_, tfoo_62_, tfoo_61_,
tfoo_60_, tfoo_59_, tfoo_58_, tfoo_57_, tfoo_56_, tfoo_55_, tfoo_54_, tfoo_53_, tfoo_52_, tfoo_51_, tfoo_50_, tfoo_49_, tfoo_48_, tfoo_47_, tfoo_46_, tfoo_45_, tfoo_44_, tfoo_43_, tfoo_42_, tfoo_41_,
tfoo_40_);
output BusEnable, rfoo_71_, rfoo_70_, rfoo_69_, rfoo_68_, rfoo_67_, rfoo_66_, rfoo_65_, rfoo_64_, rfoo_63_, rfoo_62_, rfoo_61_, rfoo_60_, rfoo_59_, rfoo_58_, rfoo_57_, rfoo_56_, rfoo_55_, rfoo_54_,
rfoo_53_, rfoo_52_, rfoo_51_, rfoo_50_, rfoo_49_, rfoo_48_, rfoo_47_, rfoo_46_, rfoo_45_, rfoo_44_, rfoo_43_, rfoo_42_, rfoo_41_, rfoo_40_, soIE5, soOE5, srdo_1_, srdo_0_;
inout BusData_8_, BusData_7_, BusData_6_, BusData_5_;
input ExtBE, Vref, bist, etfoo_7_, etfoo_6_, etfoo_5_, etfoo_4_, etfoo_3_, etfoo_2_, etfoo_1_, etfoo_0_, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, ldBD, ldBE, pd, rEn, rclk, scanM_,
sclk, se, siIO8, siOO8, srd_1_, srd_0_, tclk, tfoo_71_, tfoo_70_, tfoo_69_, tfoo_68_, tfoo_67_, tfoo_66_, tfoo_65_, tfoo_64_, tfoo_63_, tfoo_62_, tfoo_61_, tfoo_60_, tfoo_59_, tfoo_58_, tfoo_57_,
tfoo_56_, tfoo_55_, tfoo_54_, tfoo_53_, tfoo_52_, tfoo_51_, tfoo_50_, tfoo_49_, tfoo_48_, tfoo_47_, tfoo_46_, tfoo_45_, tfoo_44_, tfoo_43_, tfoo_42_, tfoo_41_, tfoo_40_;
supply1 vddA;
supply1 vddR;
supply0 gndR;
w5IOcell IO_5_(rfoo_47_, rfoo_46_, rfoo_45_, rfoo_44_, rfoo_43_, rfoo_42_, rfoo_41_, rfoo_40_, net3223, net3228, net3222, BusData_5_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_,
ictrl_0_, loadB2, loadB2_, pd, rEnB2, rEnB2_, rclk, scanM_, se, net3232, net3233, net3227, rfoo_49_, rfoo_48_, tclk, tfoo_47_, tfoo_46_, tfoo_45_, tfoo_44_, tfoo_43_, tfoo_42_, tfoo_41_, tfoo_40_);
w5IOcell IO_6_(rfoo_55_, rfoo_54_, rfoo_53_, rfoo_52_, rfoo_51_, rfoo_50_, rfoo_49_, rfoo_48_, net3232, net3233, net3227, BusData_6_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_,
ictrl_0_, loadB2, loadB2_, pd, rEnB2, rEnB2_, rclk, scanM_, se, hnl_74, hnl_75, hnl_76, net3235_0_, net3235_1_, tclk, tfoo_55_, tfoo_54_, tfoo_53_, tfoo_52_, tfoo_51_, tfoo_50_, tfoo_49_, tfoo_48_);
w5IOcell IO_7_(rfoo_63_, rfoo_62_, rfoo_61_, rfoo_60_, rfoo_59_, rfoo_58_, rfoo_57_, rfoo_56_, net3231, net3226, net3225, BusData_7_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_,
ictrl_0_, loadB1, loadB1_, pd, rEnB1, rEnB1_, rclk, scanM_, se, net3229, net3230, net3224, rfoo_65_, rfoo_64_, tclk, tfoo_63_, tfoo_62_, tfoo_61_, tfoo_60_, tfoo_59_, tfoo_58_, tfoo_57_, tfoo_56_);
w5IOcell IO_8_(rfoo_71_, rfoo_70_, rfoo_69_, rfoo_68_, rfoo_67_, rfoo_66_, rfoo_65_, rfoo_64_, net3229, net3230, net3224, BusData_8_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_,
ictrl_0_, loadB1, loadB1_, pd, rEnB1, rEnB1_, rclk, scanM_, se, hnl_77, siIO8, hnl_78, srd_1_, srd_0_, tclk, tfoo_71_, tfoo_70_, tfoo_69_, tfoo_68_, tfoo_67_, tfoo_66_, tfoo_65_, tfoo_64_);
w5CtrlR CR(loadB1, loadB1_, loadB2, loadB2_, BusEnable, rEnB1, rEnB1_, rEnB2, rEnB2_, hnl_75, hnl_76, ExtBE, Vref, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, ldBD, ldBE, rEn, scanM_,
sclk, se, hnl_79, net3225, tclk, etfoo_7_, etfoo_6_, etfoo_5_, etfoo_4_, etfoo_3_, etfoo_2_, etfoo_1_, etfoo_0_);
ppoint I104();
ppoint I103();
ppoint I102();
ppoint I101();
ppoint I100();
ppoint I99();
ppoint I98();
ppoint I97();
not #(0) U94(hnl_79, hnl_80);
not #(0) U93(hnl_80, net3226);
not #(0) U92(hnl_74, hnl_81);
not #(0) U91(hnl_81, net3231);
not #(0) U85(hnl_78, siOO8);
not #(0) U84(soOE5, net3222);
not #(0) U82(soIE5, hnl_82);
not #(0) U83(hnl_82, net3223);
not #(0) U81(hnl_83, net3228);
not #(0) U80(hnl_77, hnl_83);
not #(0) U78_0_(net3234_0_, rfoo_41_);
not #(0) U78_1_(net3234_1_, rfoo_40_);
not #(0) U77_0_(srdo_1_, net3234_0_);
not #(0) U77_1_(srdo_0_, net3234_1_);
not #(0) U76_0_(net3235_0_, net3236_0_);
not #(0) U76_1_(net3235_1_, net3236_1_);
not #(0) U75_0_(net3236_0_, rfoo_57_);
not #(0) U75_1_(net3236_1_, rfoo_56_);
endmodule

module w5SInOut (SInI, SOut, SIn, SOutI, Vref);
output SInI, SOut;
input SIn, SOutI, Vref;
supply1 vddA;
supply1 vddR;
supply0 gndR;
tranif1 N60(sinb, gndR, gndR);
resistPS R59(SIn, sinb);
tranif1 N70(SOut, gndR, hnl_84);
tranif1 N66(Vref, gndR, gndR);
tranif1 N58(SIn, gndR, gndR);
tranif0 P69(SOut, vddR, hnl_84);
tranif0 P67(Vref, vddR, vddR);
tranif0 P57(SIn, vddR, vddR);
not #(0) U55(SInI, sinbb);
not #(0) U56(sinbb, sinb);
not #(0) U68(hnl_84, SOutI);
endmodule

module w5LoadEn (ReqEn, Transmit, ldEn, Reset, SCANMode_, SynClk, bist, iotest, se, si);
output ReqEn, Transmit, ldEn;
input Reset, SCANMode_, SynClk, bist, iotest, se, si;
supply1 vddA;
supply1 vddR;
supply0 gndR;
nor #(0) U121(hnl_35, hnl_85, bist);
nor #(0) U117(hnl_40, hnl_86, hnl_36);
nor #(0) U116(ldend, hnl_40, hnl_35);
vqmsr rd(hnl_87, hnl_88, SynClk, SynClkL_);
vqmx02 I59(ReqEn, b3, hnl_87, hnl_89, SCANMode_);
vqmsrs I115(hnl_86, b3, SynClkL_, SynClk, se, se_, si);
vqmsrs lden(ldEn, ldend, SynClkL_, SynClk, se, se_, hnl_86);
not #(0) U122(hnl_36, iotest);
not #(0) U114(hnl_88, b3);
not #(0) U11(hnl_85, Reset);
not #(0) U57(Transmit, b3);
not #(0) U24(b3, ldEn);
not #(0) U74(se_, se);
not #(0) U23(SynClkL_, SynClk);
not #(0) U61(hnl_89, SCANMode_);
endmodule

module w5IOCtlA (loadBC, loadBC_, loadL1, loadL1_, loadL2, loadL2_, rEnLC, rEnLC_, rEnLD, rEnLD_, so, ldBC, ldBD, rEn, rEnC, scanM_, sclkL, sclkL_, se, si, tclkL, tclkL_);
output loadBC, loadBC_, loadL1, loadL1_, loadL2, loadL2_, rEnLC, rEnLC_, rEnLD, rEnLD_, so;
input ldBC, ldBD, rEn, rEnC, scanM_, sclkL, sclkL_, se, si, tclkL, tclkL_;
supply1 vddA;
supply1 vddR;
supply0 gndR;
ppoint I136();
ppoint I135();
ppoint I134();
ppoint I133();
nor #(0) U10(hnl_90, nldb1_, se);
nor #(0) U109(hnl_91, nlbb_, se);
nor #(0) U16(hnl_67, nldb2_, se);
nand #(0) U20(hnl_92, nldb1, hnl_93);
nand #(0) U22(hnl_94, nldb2, hnl_93);
nand #(0) U115(hnl_72, nlbb, hnl_93);
vqmxlat I99(ndr1, nrd, sclkL_, sclkL, hnl_15, scanM_, vddR);
vqmxlat I97(nrd1_, nrd_, sclkL_, sclkL, hnl_15, scanM_, gndR);
vqmxlat I100(nrd2, hnl_95, sclkL_, sclkL, hnl_15, scanM_, vddR);
vqmxlat I98(nrd2_, hnl_96, sclkL_, sclkL, hnl_15, scanM_, gndR);
vqmx02 I124(tclkd, vddR, gndR, tclkL_, tclkL);
vqmx02 I121(tclkd_, vddR, gndR, tclkL, tclkL_);
vqmx02 I91(xclk_, vddR, gndR, vddR, gndR);
vqmx02 I92(xclk, vddR, gndR, vddR, gndR);
vqmsrsz I117(nlbb, nlba, tclkL_, tclkL, se, hnl_93, hnl_70);
vqmsrsz I9(nldb1_, nlda1_, tclkL_, tclkL, se, hnl_93, nld);
vqmsrsz I25(nldb2, nlda2, tclkL_, tclkL, se, hnl_93, hnl_97);
vqmsrsz I110(nlbb_, nlba_, tclkL_, tclkL, se, hnl_93, nlb);
vqmsrsz I19(nldb1, nlda1, tclkL_, tclkL, se, hnl_93, hnl_98);
vqmsrsz I14(nldb2_, nlda2_, tclkL_, tclkL, se, hnl_93, hnl_99);
vqmsrsy I137(hnl_95, hnl_96, rEnC, sclkL, sclkL_, se, hnl_93, nrd);
vqmsrsy I65(nrd, nrd_, rEn, sclkL, sclkL_, se, hnl_93, hnl_88);
vqmsrsy I119(nlb, nlb_, ldBC, sclkL, sclkL_, se, hnl_93, hnl_100);
vqmsrsy I1(nld, nld_, ldBD, sclkL, sclkL_, se, hnl_93, si);
vqlatch I95(nlda1, nld, tclkd_, tclkd);
vqlatch I112(nlba_, nlb_, tclkd_, tclkd);
vqlatch I94(nlda2_, nld_, tclkd_, tclkd);
vqlatch I113(nlba, nlb, tclkd_, tclkd);
vqlatch I96(nlda2, nld, tclkd_, tclkd);
vqlatch I93(nlda1_, nld_, tclkd_, tclkd);
not #(0) U75(rEnLD, ndr1);
not #(0) U87(rEnLD_, nrd1_);
not #(0) U11(loadL1_, hnl_90);
not #(0) U21(loadL1, hnl_92);
not #(0) U81(rEnLC, nrd2);
not #(0) U74(rEnLC_, nrd2_);
not #(0) U89(so, hnl_101);
not #(0) U70(hnl_15, scanM_);
not #(0) U88(hnl_101, hnl_95);
not #(0) U116(loadBC, hnl_72);
not #(0) U107(loadBC_, hnl_91);
not #(0) U24(loadL2, hnl_94);
not #(0) U12(loadL2_, hnl_67);
not #(0) U108(hnl_70, nlbb_);
not #(0) U54(hnl_97, nldb1);
not #(0) U55(hnl_98, nldb2_);
not #(0) U114(hnl_88, nlbb);
not #(0) U56(hnl_99, nldb1_);
not #(0) U42(hnl_100, nldb2);
not #(0) U32(hnl_93, se);
endmodule

module w5CtrlL (ReqEn, SInI, SOut, Transmit, ldEn, loadBC, loadBC_, loadL1, loadL1_, loadL2, loadL2_, rEnLC, rEnLC_, rEnLD, rEnLD_, so_, Reset, SCANMode_, SIn, SOutI, SynClk, Vref, bist, iotest,
ldBC, ldBD, rEn, rEnC, sclk, se, si_, tclk);
output ReqEn, SInI, SOut, Transmit, ldEn, loadBC, loadBC_, loadL1, loadL1_, loadL2, loadL2_, rEnLC, rEnLC_, rEnLD, rEnLD_, so_;
input Reset, SCANMode_, SIn, SOutI, SynClk, Vref, bist, iotest, ldBC, ldBD, rEn, rEnC, sclk, se, si_, tclk;
supply1 vddA;
supply1 vddR;
supply0 gndR;
w5zerboB BZT(tclkL, tclkL_, tclk);
w5zerboB BZS(sclkL, sclkL_, sclk);
w5SInOut SIO(SInI, SOut, SIn, SOutI, Vref);
w5LoadEn LE(ReqEn, Transmit, ldEn, Reset, SCANMode_, SynClk, bist, iotest, se, hnl_102);
w5IOCtlA IOCA(loadBC, loadBC_, loadL1, loadL1_, loadL2, loadL2_, rEnLC, rEnLC_, rEnLD, rEnLD_, hnl_102, ldBC, ldBD, rEn, rEnC, SCANMode_, sclkL, sclkL_, se, hnl_103, tclkL, tclkL_);
ppoint I71();
ppoint I72();
ppoint I70();
ppoint I69();
not #(0) U68(so_, Transmit);
not #(0) U67(hnl_103, si_);
endmodule

module w5RACL (ReqEn, SInI, SOut, Transmit, brfoo_7_, brfoo_6_, brfoo_5_, brfoo_4_, brfoo_3_, brfoo_2_, brfoo_1_, brfoo_0_, ldEn, rfoo_39_, rfoo_38_, rfoo_37_, rfoo_36_, rfoo_35_, rfoo_34_, rfoo_33_,
rfoo_32_, rfoo_31_, rfoo_30_, rfoo_29_, rfoo_28_, rfoo_27_, rfoo_26_, rfoo_25_, rfoo_24_, rfoo_23_, rfoo_22_, rfoo_21_, rfoo_20_, rfoo_19_, rfoo_18_, rfoo_17_, rfoo_16_, rfoo_15_, rfoo_14_, rfoo_13_,
rfoo_12_, rfoo_11_, rfoo_10_, rfoo_9_, rfoo_8_, rfoo_7_, rfoo_6_, rfoo_5_, rfoo_4_, rfoo_3_, rfoo_2_, rfoo_1_, rfoo_0_, so_, BusCtrl, BusData_4_, BusData_3_, BusData_2_, BusData_1_, BusData_0_,
Reset, SIn, SOutI, SynClk, Vref, bist, btfoo_7_, btfoo_6_, btfoo_5_, btfoo_4_, btfoo_3_, btfoo_2_, btfoo_1_, btfoo_0_, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, iotest, ldBC, ldBD,
pd, rEn, rEnC, rclk, scanM_, sclk, se, si, srd_1_, srd_0_, tclk, tfoo_39_, tfoo_38_, tfoo_37_, tfoo_36_, tfoo_35_, tfoo_34_, tfoo_33_, tfoo_32_, tfoo_31_, tfoo_30_, tfoo_29_, tfoo_28_, tfoo_27_,
tfoo_26_, tfoo_25_, tfoo_24_, tfoo_23_, tfoo_22_, tfoo_21_, tfoo_20_, tfoo_19_, tfoo_18_, tfoo_17_, tfoo_16_, tfoo_15_, tfoo_14_, tfoo_13_, tfoo_12_, tfoo_11_, tfoo_10_, tfoo_9_, tfoo_8_, tfoo_7_,
tfoo_6_, tfoo_5_, tfoo_4_, tfoo_3_, tfoo_2_, tfoo_1_, tfoo_0_);
output ReqEn, SInI, SOut, Transmit, brfoo_7_, brfoo_6_, brfoo_5_, brfoo_4_, brfoo_3_, brfoo_2_, brfoo_1_, brfoo_0_, ldEn, rfoo_39_, rfoo_38_, rfoo_37_, rfoo_36_, rfoo_35_, rfoo_34_, rfoo_33_,
rfoo_32_, rfoo_31_, rfoo_30_, rfoo_29_, rfoo_28_, rfoo_27_, rfoo_26_, rfoo_25_, rfoo_24_, rfoo_23_, rfoo_22_, rfoo_21_, rfoo_20_, rfoo_19_, rfoo_18_, rfoo_17_, rfoo_16_, rfoo_15_, rfoo_14_, rfoo_13_,
rfoo_12_, rfoo_11_, rfoo_10_, rfoo_9_, rfoo_8_, rfoo_7_, rfoo_6_, rfoo_5_, rfoo_4_, rfoo_3_, rfoo_2_, rfoo_1_, rfoo_0_, so_;
inout BusCtrl, BusData_4_, BusData_3_, BusData_2_, BusData_1_, BusData_0_;
input Reset, SIn, SOutI, SynClk, Vref, bist, btfoo_7_, btfoo_6_, btfoo_5_, btfoo_4_, btfoo_3_, btfoo_2_, btfoo_1_, btfoo_0_, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, iotest, ldBC,
ldBD, pd, rEn, rEnC, rclk, scanM_, sclk, se, si, srd_1_, srd_0_, tclk, tfoo_39_, tfoo_38_, tfoo_37_, tfoo_36_, tfoo_35_, tfoo_34_, tfoo_33_, tfoo_32_, tfoo_31_, tfoo_30_, tfoo_29_, tfoo_28_,
tfoo_27_, tfoo_26_, tfoo_25_, tfoo_24_, tfoo_23_, tfoo_22_, tfoo_21_, tfoo_20_, tfoo_19_, tfoo_18_, tfoo_17_, tfoo_16_, tfoo_15_, tfoo_14_, tfoo_13_, tfoo_12_, tfoo_11_, tfoo_10_, tfoo_9_, tfoo_8_,
tfoo_7_, tfoo_6_, tfoo_5_, tfoo_4_, tfoo_3_, tfoo_2_, tfoo_1_, tfoo_0_;
supply1 vddA;
supply1 vddR;
supply0 gndR;
w5IOcell IO_4_(rfoo_39_, rfoo_38_, rfoo_37_, rfoo_36_, rfoo_35_, rfoo_34_, rfoo_33_, rfoo_32_, net3611, net3612, net3602, BusData_4_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_,
ictrl_0_, loadA2, loadA2_, pd, rEnA1, rEnA1_, rclk, scanM_, se, hnl_104, si, hnl_105, srd_1_, srd_0_, tclk, tfoo_39_, tfoo_38_, tfoo_37_, tfoo_36_, tfoo_35_, tfoo_34_, tfoo_33_, tfoo_32_);
w5IOcell IO_0_(rfoo_7_, rfoo_6_, rfoo_5_, rfoo_4_, rfoo_3_, rfoo_2_, rfoo_1_, rfoo_0_, net3604, net3601, so_, BusData_0_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_,
loadA1, loadA1_, pd, rEnA1, rEnA1_, rclk, scanM_, se, net3605, net3606, net3600, rfoo_9_, rfoo_8_, tclk, tfoo_7_, tfoo_6_, tfoo_5_, tfoo_4_, tfoo_3_, tfoo_2_, tfoo_1_, tfoo_0_);
w5IOcell IO_1_(rfoo_15_, rfoo_14_, rfoo_13_, rfoo_12_, rfoo_11_, rfoo_10_, rfoo_9_, rfoo_8_, net3605, net3606, net3600, BusData_1_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_,
ictrl_0_, loadA1, loadA1_, pd, rEnA1, rEnA1_, rclk, scanM_, se, net3607, net3608, net3599, rfoo_17_, rfoo_16_, tclk, tfoo_15_, tfoo_14_, tfoo_13_, tfoo_12_, tfoo_11_, tfoo_10_, tfoo_9_, tfoo_8_);
w5IOcell IO_2_(rfoo_23_, rfoo_22_, rfoo_21_, rfoo_20_, rfoo_19_, rfoo_18_, rfoo_17_, rfoo_16_, net3607, net3608, net3599, BusData_2_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_,
ictrl_0_, loadA1, loadA1_, pd, rEnA1, rEnA1_, rclk, scanM_, se, net3609, net3610, net3598, rfoo_25_, rfoo_24_, tclk, tfoo_23_, tfoo_22_, tfoo_21_, tfoo_20_, tfoo_19_, tfoo_18_, tfoo_17_, tfoo_16_);
w5IOcell IO_3_(rfoo_31_, rfoo_30_, rfoo_29_, rfoo_28_, rfoo_27_, rfoo_26_, rfoo_25_, rfoo_24_, net3609, net3610, net3598, BusData_3_, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_,
ictrl_0_, loadA1, loadA1_, pd, rEnA1, rEnA1_, rclk, scanM_, se, hnl_106, hnl_107, hnl_108, net3603_0_, net3603_1_, tclk, tfoo_31_, tfoo_30_, tfoo_29_, tfoo_28_, tfoo_27_, tfoo_26_, tfoo_25_,
tfoo_24_);
w5IOcell BC(brfoo_7_, brfoo_6_, brfoo_5_, brfoo_4_, brfoo_3_, brfoo_2_, brfoo_1_, brfoo_0_, hnl_109, hnl_110, hnl_111, BusCtrl, Vref, bist, ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_,
loadBC, loadBC_, pd, rEnA2, rEnA2_, sclk, scanM_, se, net3611, net3612, net3602, rfoo_33_, rfoo_32_, tclk, btfoo_7_, btfoo_6_, btfoo_5_, btfoo_4_, btfoo_3_, btfoo_2_, btfoo_1_, btfoo_0_);
w5CtrlL CL(ReqEn, SInI, SOut, Transmit, ldEn, loadBC, loadBC_, loadA1, loadA1_, loadA2, loadA2_, rEnA2, rEnA2_, rEnA1, rEnA1_, hnl_108, Reset, scanM_, SIn, SOutI, SynClk, Vref, bist, iotest, ldBC,
ldBD, rEn, rEnC, sclk, se, hnl_111, tclk);
ppoint I90();
ppoint I89();
ppoint I88();
ppoint I87();
ppoint I86();
ppoint I85();
ppoint I84();
ppoint I83();
ppoint I82();
ppoint I81();
ppoint I80();
ppoint I79();
not #(0) U78(hnl_107, hnl_64);
not #(0) U77(hnl_64, hnl_110);
not #(0) U76(hnl_106, hnl_112);
not #(0) U75(hnl_112, hnl_109);
not #(0) U69_0_(net3603_0_, net3597_0_);
not #(0) U69_1_(net3603_1_, net3597_1_);
not #(0) U68_0_(net3597_0_, brfoo_1_);
not #(0) U68_1_(net3597_1_, brfoo_0_);
not #(0) U66(hnl_113, net3601);
not #(0) U65(hnl_104, hnl_113);
not #(0) U63(hnl_105, net3604);
endmodule

module vqmsrsR (Q, D, clk, clk_, rst, rstb, se, se_, si);
output Q;
input D, clk, clk_, rst, rstb, se, se_, si;
supply1 vddA;
supply1 vddR;
supply0 gndR;
tranif1 U28(gndR, hnl_9, rst);
tranif0 U29(hnl_1, vddR, rstb);
latW U4(hnl_8, hnl_9);
latW U7(Q, hnl_1);
cxfr U21(sh, se, se_, si);
cxfr U14(sh, se_, se, D);
cxfr U2(hnl_9, clk_, clk, sh);
cxfr U5(hnl_1, clk, clk_, hnl_8);
endmodule

module w5Prsclr (IctrlLd, ictrlOn, slowClk_, so, CCtlLd, SCANClk, SCANMode_, SynClk, pd, reset, se, si);
output IctrlLd, ictrlOn, slowClk_, so;
input CCtlLd, SCANClk, SCANMode_, SynClk, pd, reset, se, si;
supply1 vddA;
supply1 vddR;
supply0 gndR;
vqlatch I55(ion, c31_, SynClk, SynClkL_);
vqmsrs I58(IctrlLd, CCtlLd, SynClkL_, SynClk, se, se_, hnl_114);
nor #(0) U43(hnl_66, hnl_115, hnl_100);
vqmsrsR Q4(hnl_114, hnl_116, SynClkL_, SynClk, reset, hnl_105, se, se_, hnl_117);
vqmsrsR Q3(hnl_117, hnl_118, SynClkL_, SynClk, reset, hnl_105, se, se_, hnl_119);
vqmsrsR Q2(hnl_119, hnl_120, SynClkL_, SynClk, reset, hnl_105, se, se_, hnl_121);
vqmsrsR Q1(hnl_121, hnl_122, SynClkL_, SynClk, reset, hnl_105, se, se_, hnl_123);
vqmsrsR Q0(hnl_123, hnl_71, SynClkL_, SynClk, reset, hnl_105, se, se_, si);
nand #(0) U46(sloc1, SynClk, hnl_114, hnl_66);
nand #(0) U42(hnl_100, hnl_123, hnl_121, hnl_119);
nand #(0) U69(hnl_14, ion, hnl_84);
nand #(0) U45(c31_, hnl_66, hnl_114);
nand #(0) U39(hnl_124, hnl_121, hnl_123);
vqmx02 I52(slowClk_, sloc1, hnl_125, SCANMode_, hnl_126);
vqmx02 I32(hnl_116, hnl_127, hnl_114, hnl_128, hnl_66);
vqmx02 I31(hnl_118, hnl_115, hnl_117, hnl_100, hnl_129);
vqmx02 I30(hnl_120, hnl_62, hnl_119, hnl_124, hnl_130);
vqmx02 I29(hnl_122, hnl_57, hnl_121, hnl_71, hnl_123);
not #(0) U70(ictrlOn, hnl_14);
not #(0) U68(hnl_84, pd);
not #(0) U50(hnl_125, SCANClk);
not #(0) U53(hnl_126, SCANMode_);
not #(0) U56(so, hnl_89);
not #(0) U61(hnl_89, IctrlLd);
not #(0) U44(hnl_128, hnl_66);
not #(0) U41(hnl_129, hnl_100);
not #(0) U40(hnl_130, hnl_124);
not #(0) U37(hnl_127, hnl_114);
not #(0) U36(hnl_115, hnl_117);
not #(0) U35(hnl_62, hnl_119);
not #(0) U34(hnl_57, hnl_121);
not #(0) U38(hnl_71, hnl_123);
not #(0) U27(se_, se);
not #(0) U63(hnl_105, reset);
not #(0) U10(SynClkL_, SynClk);
endmodule

module w5PreLR (bcsint_3_, bcsint_2_, bcsint_1_, bcsint_0_, bdsint_3_, bdsint_2_, bdsint_1_, bdsint_0_, rcsint_3_, rcsint_2_, rcsint_1_, rcsint_0_, rdsint_3_, rdsint_2_, rdsint_1_, rdsint_0_,
BCSel_3_, BCSel_2_, BCSel_1_, BCSel_0_, BDSel_3_, BDSel_2_, BDSel_1_, BDSel_0_, RCSel_3_, RCSel_2_, RCSel_1_, RCSel_0_, RDSel_3_, RDSel_2_, RDSel_1_, RDSel_0_, bist);
output bcsint_3_, bcsint_2_, bcsint_1_, bcsint_0_, bdsint_3_, bdsint_2_, bdsint_1_, bdsint_0_, rcsint_3_, rcsint_2_, rcsint_1_, rcsint_0_, rdsint_3_, rdsint_2_, rdsint_1_, rdsint_0_;
input BCSel_3_, BCSel_2_, BCSel_1_, BCSel_0_, BDSel_3_, BDSel_2_, BDSel_1_, BDSel_0_, RCSel_3_, RCSel_2_, RCSel_1_, RCSel_0_, RDSel_3_, RDSel_2_, RDSel_1_, RDSel_0_, bist;
supply1 vddA;
supply1 vddR;
supply0 gndR;
nor #(0) U95(hnl_131, RCSel_2_, bist);
nor #(0) U19(hnl_63, RDSel_2_, bist);
nor #(0) U15(hnl_132, BDSel_0_, bist);
nor #(0) U7(hnl_133, BCSel_0_, bist);
not #(0) U103(rcsint_2_, hnl_131);
not #(0) U102(rcsint_3_, hnl_134);
not #(0) U98(rcsint_0_, hnl_135);
not #(0) U96(rcsint_1_, hnl_136);
not #(0) U25(bistb, bist);
not #(0) U24(rdsint_0_, hnl_55);
not #(0) U22(rdsint_1_, hnl_137);
not #(0) U20(rdsint_2_, hnl_63);
not #(0) U18(rdsint_3_, hnl_138);
not #(0) U16(bdsint_0_, hnl_132);
not #(0) U14(bdsint_1_, hnl_5);
not #(0) U12(bdsint_2_, hnl_85);
not #(0) U10(bdsint_3_, hnl_73);
not #(0) U8(bcsint_0_, hnl_133);
not #(0) U6(bcsint_1_, hnl_139);
not #(0) U4(bcsint_2_, hnl_4);
not #(0) U2(bcsint_3_, hnl_140);
nand #(0) U104(hnl_135, RCSel_0_, bistb);
nand #(0) U100(hnl_134, RCSel_3_, bistb);
nand #(0) U99(hnl_136, RCSel_1_, bistb);
nand #(0) U23(hnl_55, RDSel_0_, bistb);
nand #(0) U21(hnl_137, RDSel_1_, bistb);
nand #(0) U17(hnl_138, RDSel_3_, bistb);
nand #(0) U13(hnl_5, BDSel_1_, bistb);
nand #(0) U11(hnl_85, BDSel_2_, bistb);
nand #(0) U9(hnl_73, BDSel_3_, bistb);
nand #(0) U5(hnl_139, BCSel_1_, bistb);
nand #(0) U3(hnl_4, BCSel_2_, bistb);
nand #(0) U1(hnl_140, BCSel_3_, bistb);
endmodule

module w5LdREn (ldBC, ldBD, ldBE, rEn, rEnC, so, BCSel_3_, BCSel_2_, BCSel_1_, BCSel_0_, BDSel_3_, BDSel_2_, BDSel_1_, BDSel_0_, BESel_3_, BESel_2_, BESel_1_, BESel_0_, RCSel_3_, RCSel_2_, RCSel_1_,
RCSel_0_, REnSel_3_, REnSel_2_, REnSel_1_, REnSel_0_, ldEn, samplse, samplse_, sclk, se, si);
output ldBC, ldBD, ldBE, rEn, rEnC, so;
input BCSel_3_, BCSel_2_, BCSel_1_, BCSel_0_, BDSel_3_, BDSel_2_, BDSel_1_, BDSel_0_, BESel_3_, BESel_2_, BESel_1_, BESel_0_, RCSel_3_, RCSel_2_, RCSel_1_, RCSel_0_, REnSel_3_, REnSel_2_, REnSel_1_,
REnSel_0_, ldEn, samplse, samplse_, sclk, se, si;
supply1 vddA;
supply1 vddR;
supply0 gndR;
w5zerboB BZS(sclkL, sclkL_, sclk);
ppoint I88();
ppoint I87();
nand #(0) U45(hnl_141, ldEn, hnl_142);
nand #(0) U69(hnl_14, ldEn, hnl_143);
nand #(0) U63(hnl_105, ldEn, hnl_144);
nor #(0) U89(hnl_145, hnl_128, hnl_146);
nor #(0) U34(hnl_57, hnl_128, hnl_147);
nor #(0) U31(hnl_68, hnl_128, hnl_100);
nor #(0) U64(hnl_148, hnl_128, hnl_149);
nor #(0) U59(hnl_150, hnl_128, hnl_127);
vqmsrs I98(hnl_151, RCSel_3_, sclkL, sclkL_, samplse_, samplse, hnl_145);
vqmsrs I95(hnl_152, RCSel_2_, sclkL, sclkL_, samplse_, samplse, hnl_151);
vqmsrs I92(rEnC, RCSel_0_, sclkL, sclkL_, samplse_, samplse, hnl_153);
vqmsrs I90(hnl_153, RCSel_1_, sclkL, sclkL_, samplse_, samplse, hnl_152);
vqmsrs I23(hnl_154, REnSel_1_, sclkL, sclkL_, samplse_, samplse, hnl_155);
vqmsrs I27(hnl_156, REnSel_3_, sclkL, sclkL_, samplse_, samplse, hnl_57);
vqmsrs I47(hnl_157, BESel_3_, sclkL, sclkL_, samplse_, samplse, hnl_150);
vqmsrs I11(hnl_158, BDSel_2_, sclkL, sclkL_, samplse_, samplse, hnl_159);
vqmsrs I10(hnl_159, BDSel_3_, sclkL, sclkL_, samplse_, samplse, hnl_68);
vqmsrs I48(hnl_160, BESel_2_, sclkL, sclkL_, samplse_, samplse, hnl_157);
vqmsrs I74(hnl_161, BCSel_3_, sclkL, sclkL_, samplse_, samplse, hnl_148);
vqmsrs I13(hnl_162, BDSel_1_, sclkL, sclkL_, samplse_, samplse, hnl_158);
vqmsrs I26(hnl_155, REnSel_2_, sclkL, sclkL_, samplse_, samplse, hnl_156);
vqmsrs I73(hnl_163, BCSel_2_, sclkL, sclkL_, samplse_, samplse, hnl_161);
vqmsrs I67(hnl_164, BCSel_1_, sclkL, sclkL_, samplse_, samplse, hnl_163);
vqmsrs I61(hnl_165, BESel_1_, sclkL, sclkL_, samplse_, samplse, hnl_160);
vqmsrs I25(rEn, REnSel_0_, sclkL, sclkL_, samplse_, samplse, hnl_154);
vqmsrs I54(hnl_144, BESel_0_, sclkL, sclkL_, samplse_, samplse, hnl_165);
vqmsrs I43(hnl_142, BDSel_0_, sclkL, sclkL_, samplse_, samplse, hnl_162);
vqmsrs I68(hnl_143, BCSel_0_, sclkL, sclkL_, samplse_, samplse, hnl_164);
not #(0) U97(hnl_147, rEnC);
not #(0) U96(hnl_146, si);
not #(0) U44(hnl_128, se);
not #(0) U42(hnl_100, rEn);
not #(0) U65(so, hnl_113);
not #(0) U37(hnl_127, hnl_142);
not #(0) U66(hnl_113, hnl_143);
not #(0) U58(hnl_149, hnl_144);
not #(0) U78(ldBD, hnl_141);
not #(0) U77(ldBE, hnl_105);
not #(0) U76(ldBC, hnl_14);
endmodule

module w5ESDClk (pad);
inout pad;
supply1 vddA;
supply1 vddR;
supply0 gndR;
tranif0 P34(pad, vddR, vddR);
tranif1 N33(pad, gndR, gndR);
endmodule

module w5Div (fd, smpl, smpl_, syncout, PhStall, Reset, Syncin, rclkL, rclkL_);
output fd, smpl, smpl_, syncout;
input PhStall, Reset, Syncin, rclkL, rclkL_;
supply1 vddA;
supply1 vddR;
supply0 gndR;
msrY Q0(syncout, fd, rclkL, rclkL_);
nand #(0) U29(fd, hnl_166, hnl_121);
nand #(0) U33(hnl_166, hnl_167, hnl_57);
cxfr U36(hnl_168, hnl_169, hnl_170, hnl_171);
tranif1 N37(hnl_168, gndR, hnl_170);
not #(0) U15(smpl, smpl_);
vqmsr S7(hnl_167, hnl_168, rclkL, rclkL_);
vqmsr S4(hnl_170, hnl_171, rclkL, rclkL_);
vqmsr S2(hnl_172, PhStall, syncout, hnl_173);
vqmsr S3(hnl_171, hnl_172, syncout, hnl_173);
vqmsr Q1(hnl_121, Syncin, rclkL, rclkL_);
nand #(1) U14(smpl_, syncout, hnl_121);
not #(0) U34(hnl_57, Reset);
not #(0) S5(hnl_169, hnl_170);
not #(0) S1(hnl_173, syncout);
endmodule

module w5Clks2 (SCANM_, SynClk, SynClkFd, Synint, samplse, samplse_, se, so, PhStall, Reset, SCANCLK, SCANEn, SCANMode, SynClkIn, r2s, r2s_, si);
output SCANM_, SynClk, SynClkFd, Synint, samplse, samplse_, se, so;
input PhStall, Reset, SCANCLK, SCANEn, SCANMode, SynClkIn, r2s, r2s_, si;
supply1 vddA;
supply1 vddR;
supply0 gndR;
w5Div D(hnl_174, hnl_175, hnl_176, sy4, PhStall, Reset, SynClkIn, r2s, r2s_);
msrY I298(SynClkFd, hnl_174, r2s, r2s_);
nand #(1) U145(hnl_177, SCANMode, SCANEn);
vqmsr I94(hnl_178, si, SCANCLK, hnl_179);
not #(0) U331(hnl_179, SCANCLK);
not #(0) U95(hnl_131, hnl_178);
not #(0) U96(so, hnl_131);
nor #(0) U92(hnl_74, SCANEn, hnl_131);
not #(0) U91(Synint, sy6);
not #(0) U211(sy6, sy5);
not #(0) U306(SynClk, hnl_180);
not #(0) U307(hnl_180, sy5);
not #(0) U147(SCANM_, SCANMode);
not #(0) U144(se, hnl_177);
not #(0) U93(hnl_80, hnl_74);
not #(0) U311(hnl_181, hnl_182);
not #(0) U310(samplse, hnl_181);
not #(0) U98(hnl_183, hnl_184);
not #(0) U293(samplse_, hnl_183);
vqmxfr I253(sy5, sy4, hnl_179, SCANM_, SCANMode);
vqmxfr I251(hnl_184, hnl_176, hnl_80, SCANM_, SCANMode);
vqmxfr I309(hnl_182, hnl_175, hnl_74, SCANM_, SCANMode);
endmodule

module w5Clks (SCANM_, SynClk, SynClkFd, Synint, pd, rclk, rclkpll, samplse, samplse_, sclk, se, so, tclk, tclkpll, ByPSel, ByPass, PhStall, PwrUp, Reset, SCANClk, SCANEn, SCANMode, StopR, StopT,
SynClkIn, rclkASIC, rclkBus, rclkDrv_, si, tclkASIC, tclkBus, tclkDrv_);
output SCANM_, SynClk, SynClkFd, Synint, pd, rclk, rclkpll, samplse, samplse_, sclk, se, so, tclk, tclkpll;
input ByPSel, ByPass, PhStall, PwrUp, Reset, SCANClk, SCANEn, SCANMode, StopR, StopT, SynClkIn, rclkASIC, rclkBus, rclkDrv_, si, tclkASIC, tclkBus, tclkDrv_;
supply1 vddA;
supply1 vddR;
supply0 gndR;
w5Clks2 CK2(SCANM_, SynClk, SynClkFd, Synint, samplse, samplse_, se, so, PhStall, Reset, SCANClk, SCANEn, SCANMode, SynClkIn, r2s, r2s_, si);
w5zerboB BZ(hnl_185, hnl_186, rout);
vqmx02 I542(hnl_187, rclkASIC, rclkBus, ByPSel_, ByPSel);
vqmx02 I540(hnl_188, tclkASIC, tclkBus, ByPSel_, ByPSel);
nand #(0) U500(hnl_189, hnl_190, hnl_126, hnl_191);
nor #(0) U409(hnl_192, ByPass, SCANMode);
tranif0 P427(t3, vddR, hnl_193);
tranif1 N486(s3, gndR, hnl_194);
tranif1 N485(r3, gndR, hnl_195);
nand #(0) U431(hnl_193, hnl_191, hnl_126);
nand #(0) U504(hnl_196, hnl_190, hnl_126);
nand #(0) U401(pd, hnl_197, PwrUp);
not #(0) U406(ByPSel_, ByPSel);
not #(0) U425(hnl_198, hnl_193);
not #(0) U501(hnl_194, hnl_189);
not #(0) U502(hnl_195, hnl_196);
not #(0) U407(hnl_199, SCANClk);
not #(0) U506(Synint_, Synint);
not #(0) U400(hnl_197, StopR);
not #(0) U26(tclkpll, tl4);
not #(0) U524(r0, rout);
not #(0) U539(tl4, tl3);
not #(0) U516(s4, s3);
not #(0) U536(hnl_200, tl4);
not #(0) U538(hnl_201, tl4);
not #(0) U446(sclk, s4);
not #(0) U513(r4, r3);
not #(0) U432(sl4, sl3);
not #(0) U533(hnl_202, sl4);
not #(0) U534(hnl_203, sl4);
not #(0) U531(rdv1, rdv0);
not #(0) U532(rdv0, rclkDrv_);
not #(0) U34(rclkpll, sl4);
not #(0) U433(r2, r1);
not #(0) U525(t0, tout);
not #(0) U523(t1, t0);
not #(0) U419(t2, t1);
not #(0) U522(r1, r0);
not #(0) U509(r2s_, hnl_186);
not #(0) U508(r2s, hnl_185);
not #(0) U518(t4, t3);
not #(0) U36(rclk, r4);
not #(0) U28(tclk, t4);
not #(0) U410(hnl_204, hnl_192);
not #(0) U53(hnl_126, SCANMode);
cxfr U25(tl3, vddR, gndR, t2);
cxfr U444(s3, hnl_189, hnl_194, r2);
cxfr U435(r3, hnl_196, hnl_195, r2);
cxfr U33(sl3, vddR, gndR, r2);
cxfr U423(t3, hnl_193, hnl_198, t2);
vqmxfr I413(tout, tclkDrv_, hnl_205, hnl_192, hnl_204);
vqmxfr U45(rout, rdv1, hnl_206, hnl_192, hnl_204);
vqmxfr I417(hnl_205, hnl_188, SCANClk, hnl_126, SCANMode);
vqmxfr I405(hnl_206, hnl_187, hnl_199, hnl_126, SCANMode);
vqmsr I503(hnl_190, StopR, Synint, Synint_);
vqmsr U4(hnl_191, StopT, Synint, Synint_);
endmodule

module w5RACC (SCANM_, SynClk, SynClkFd, Synint, ictrlLd, ictrlOn, ldBC, ldBD, ldBE, pd, rEn, rEnC, rclk, sclk, se, slowClk_, so, tclk, BCSel_3_, BCSel_2_, BCSel_1_, BCSel_0_, BDSel_3_, BDSel_2_,
BDSel_1_, BDSel_0_, BESel_3_, BESel_2_, BESel_1_, BESel_0_, BusClk, ByPSel, ByPass, CCtlLd, PhStall, PwrUp, RCSel_3_, RCSel_2_, RCSel_1_, RCSel_0_, REnSel_3_, REnSel_2_, REnSel_1_, REnSel_0_, Reset,
SCANClk, SCANEn, SCANMode, StopR, StopT, SynClkIn, Vref, bist, ldEn, rclkASIC, si, tclkASIC);
output SCANM_, SynClk, SynClkFd, Synint, ictrlLd, ictrlOn, ldBC, ldBD, ldBE, pd, rEn, rEnC, rclk, sclk, se, slowClk_, so, tclk;
input BCSel_3_, BCSel_2_, BCSel_1_, BCSel_0_, BDSel_3_, BDSel_2_, BDSel_1_, BDSel_0_, BESel_3_, BESel_2_, BESel_1_, BESel_0_, BusClk, ByPSel, ByPass, CCtlLd, PhStall, PwrUp, RCSel_3_, RCSel_2_,
RCSel_1_, RCSel_0_, REnSel_3_, REnSel_2_, REnSel_1_, REnSel_0_, Reset, SCANClk, SCANEn, SCANMode, StopR, StopT, SynClkIn, Vref, bist, ldEn, rclkASIC, si, tclkASIC;
supply1 vddA;
supply1 vddR;
supply0 gndR;
w5DLL L(tclkDrv_, rclkDrv_, tclkBus, rclkBus, ByPass, hnl_207, hnl_207, hnl_208, PwrUp, tclkpll, rclkpll);
w5Prsclr P(ictrlLd, ictrlOn, slowClk_, so, CCtlLd, SCANClk, SCANM_, Synint, pd, Reset, se, hnl_209);
w5PreLR PLR(hnl_210, hnl_211, hnl_212, hnl_213, hnl_214, hnl_215, hnl_216, hnl_217, hnl_218, hnl_219, hnl_220, hnl_221, hnl_222, hnl_223, hnl_224, hnl_225, BCSel_3_, BCSel_2_, BCSel_1_, BCSel_0_,
BDSel_3_, BDSel_2_, BDSel_1_, BDSel_0_, RCSel_3_, RCSel_2_, RCSel_1_, RCSel_0_, REnSel_3_, REnSel_2_, REnSel_1_, REnSel_0_, bist);
w5LdREn LR(ldBC, ldBD, ldBE, rEn, rEnC, hnl_209, hnl_210, hnl_211, hnl_212, hnl_213, hnl_214, hnl_215, hnl_216, hnl_217, BESel_3_, BESel_2_, BESel_1_, BESel_0_, hnl_218, hnl_219, hnl_220, hnl_221,
hnl_222, hnl_223, hnl_224, hnl_225, ldEn, samplse, samplse_, sclk, se, hnl_226);
w5ESDClk ECR(BusClk);
w5Clks K(SCANM_, SynClk, SynClkFd, Synint, pd, rclk, rclkpll, samplse, samplse_, sclk, se, hnl_226, tclk, tclkpll, ByPSel, ByPass, PhStall, PwrUp, Reset, SCANClk, SCANEn, SCANMode, StopR, StopT,
SynClkIn, rclkASIC, rclkBus, rclkDrv_, si, tclkASIC, tclkBus, tclkDrv_);
ppoint I85();
ppoint I81();
ppoint I80();
ppoint I74();
ppoint I77();
ppoint I76();
ppoint I75();
capN C1(vddA, gndR);
resistPS R65(Vref, hnl_208);
resistPS R62(BusClk, hnl_207);
endmodule

module w5UDcell (cOut, ictrl, so, tDrv_, Din, carryIn, ictrlEn, ictrlLd, ictrlOn, se, se_, si, slowClk, slowClk_, up);
output cOut, ictrl, so, tDrv_;
input Din, carryIn, ictrlEn, ictrlLd, ictrlOn, se, se_, si, slowClk, slowClk_, up;
supply1 vddA;
supply1 vddR;
supply0 gndR;
nand #(0) U26(tDrv_, hnl_227, ictrlOn);
nand #(0) U21(hnl_137, hnl_228, carryIn);
vqlatch I2(ictrl, so, ictrlLd, hnl_56);
vqmsrs I1(so, hnl_229, slowClk_, slowClk, se, se_, si);
vqmx02 I4(hnl_230, hnl_227, so, carryIn, hnl_67);
vqmx02 I5(hnl_228, hnl_227, so, hnl_92, up);
vqmx02 I3(hnl_229, Din, hnl_230, hnl_132, ictrlEn);
not #(0) U18(hnl_227, so);
not #(0) U22(cOut, hnl_137);
not #(0) U20(hnl_92, up);
not #(0) U16(hnl_67, carryIn);
not #(0) U15(hnl_132, ictrlEn);
not #(0) U24(hnl_56, ictrlLd);
endmodule

module vqao21 (Y, A1, A2, B);
output Y;
input A1, A2, B;
supply1 vddA;
supply1 vddR;
supply0 gndR;
tranif0 P2(Y, hnl_231, A2);
tranif0 P1(Y, hnl_231, A1);
tranif0 P3(hnl_231, vddR, B);
tranif1 N3(Y, gndR, B);
tranif1 N2(hnl_232, gndR, A2);
tranif1 N1(Y, hnl_232, A1);
endmodule

module w5UDCntr (ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, op_5_, op_4_, op_3_, op_2_, op_1_, op_0_, so, Din_5_, Din_4_, Din_3_, Din_2_, Din_1_, Din_0_, IctrlEn, IctrlLd, carryIn,
ictrlOn, scanM_, se, si, slowClk, slowClk_, up);
output ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, op_5_, op_4_, op_3_, op_2_, op_1_, op_0_, so;
input Din_5_, Din_4_, Din_3_, Din_2_, Din_1_, Din_0_, IctrlEn, IctrlLd, carryIn, ictrlOn, scanM_, se, si, slowClk, slowClk_, up;
supply1 vddA;
supply1 vddR;
supply0 gndR;
w5UDcell Q0(hnl_233, hnl_234, hnl_235, hnl_236, Din_0_, icarryin, IctrlEn, IctrlLd, ictrlOn, se, se_, si, slowClk, slowClk_, up);
w5UDcell Q1(hnl_237, hnl_238, hnl_239, hnl_240, Din_1_, hnl_233, IctrlEn, IctrlLd, ictrlOn, se, se_, hnl_235, slowClk, slowClk_, up);
w5UDcell Q2(hnl_241, hnl_242, hnl_243, hnl_244, Din_2_, hnl_237, IctrlEn, IctrlLd, ictrlOn, se, se_, hnl_239, slowClk, slowClk_, up);
w5UDcell Q3(hnl_245, hnl_246, hnl_247, hnl_248, Din_3_, hnl_241, IctrlEn, IctrlLd, ictrlOn, se, se_, hnl_243, slowClk, slowClk_, up);
w5UDcell Q4(hnl_249, hnl_250, hnl_251, hnl_252, Din_4_, hnl_245, IctrlEn, IctrlLd, ictrlOn, se, se_, hnl_247, slowClk, slowClk_, up);
w5UDcell Q5(hnl_253, hnl_254, hnl_255, hnl_256, Din_5_, hnl_249, IctrlEn, IctrlLd, ictrlOn, se, se_, hnl_251, slowClk, slowClk_, up);
vqmsr I49(hnl_257, hnl_253, hnl_126, ictrlOn);
vqao21 U54(icarryin, scanM_, hnl_257, hnl_258);
not #(0) U33(ictrl_0_, hnl_93);
not #(0) U31(ictrl_1_, hnl_259);
not #(0) U26(ictrl_3_, hnl_65);
not #(0) U25(ictrl_4_, hnl_56);
not #(0) U23(ictrl_5_, hnl_94);
not #(0) U22(hnl_94, hnl_254);
not #(0) U53(hnl_126, ictrlOn);
not #(0) U32(hnl_93, hnl_234);
not #(0) U30(hnl_259, hnl_238);
not #(0) U29(hnl_260, hnl_242);
not #(0) U28(ictrl_2_, hnl_260);
not #(0) U27(hnl_65, hnl_246);
not #(0) U24(hnl_56, hnl_250);
not #(0) U51(hnl_258, carryIn);
not #(0) U50(so, hnl_261);
not #(0) U46(hnl_261, hnl_255);
not #(0) U39(op_5_, hnl_256);
not #(0) U38(op_4_, hnl_252);
not #(0) U37(op_3_, hnl_248);
not #(0) U36(op_2_, hnl_244);
not #(0) U35(op_1_, hnl_240);
not #(0) U34(op_0_, hnl_236);
not #(0) U42(se_, se);
endmodule

module w5CCFsm (add, carryIn, so, sub, ictrlOn, reset, se, si, slowClk, slowClk_, up);
output add, carryIn, so, sub;
input ictrlOn, reset, se, si, slowClk, slowClk_, up;
supply1 vddA;
supply1 vddR;
supply0 gndR;
nor #(0) U9(hnl_73, o1, o0);
vqmsrsR S0(o0, i0, slowClk_, slowClk, reset, hnl_115, se, hnl_166, si);
vqmsrsR S1(o1, i1, slowClk_, slowClk, reset, hnl_115, se, hnl_166, o0);
nand #(0) U13(carryIn, hnl_4, hnl_8);
nand #(0) U3(hnl_4, up, o1);
nand #(0) U4(hnl_8, hnl_85, o0);
nand #(0) U20(hnl_92, o1, ictrlOn);
nand #(0) U17(hnl_138, o0, ictrlOn);
nand #(0) U5(hnl_139, hnl_73, hnl_85);
nand #(0) U6(hnl_262, up, hnl_73);
not #(0) U29(so, hnl_58);
not #(0) U28(hnl_58, o1);
not #(0) U19(add, hnl_92);
not #(0) U16(sub, hnl_138);
not #(0) U36(hnl_115, reset);
not #(0) U33(hnl_166, se);
not #(0) U11(hnl_85, up);
not #(0) U8(i0, hnl_139);
not #(0) U7(i1, hnl_262);
endmodule

module w5CCtrl (ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, so, CCtlEn, CCtlI_5_, CCtlI_4_, CCtlI_3_, CCtlI_2_, CCtlI_1_, CCtlI_0_, CCtlPgm, IctrlLd, Vref, ictrlOn, pd, reset, scanM_,
se, si, slowClk_);
output ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, so;
input CCtlEn, CCtlI_5_, CCtlI_4_, CCtlI_3_, CCtlI_2_, CCtlI_1_, CCtlI_0_, CCtlPgm, IctrlLd, Vref, ictrlOn, pd, reset, scanM_, se, si, slowClk_;
supply1 vddA;
supply1 vddR;
supply0 gndR;
w5UDCntr C(ictrl_5_, ictrl_4_, ictrl_3_, ictrl_2_, ictrl_1_, ictrl_0_, op_5_, op_4_, op_3_, op_2_, op_1_, op_0_, hnl_263, CCtlI_5_, CCtlI_4_, CCtlI_3_, CCtlI_2_, CCtlI_1_, CCtlI_0_, CCtlEn, IctrlLd,
hnl_264, ictrlOn, scanM_, se, si, slowClk, slowClk_, hnl_265);
w5ISBiGn BG(hnl_266, pd);
w5CCFsm F(hnl_267, hnl_264, so, hnl_268, ictrlOn, reset, se, hnl_263, slowClk, slowClk_, hnl_265);
w5CCAnal A(hnl_265, op_5_, op_4_, op_3_, op_2_, op_1_, op_0_, hnl_268, hnl_267, CCtlPgm, hnl_266, Vref, ictrlOn, slowClk, scanM_);
not #(0) U54(slowClk, slowClk_);
endmodule

module vqmsrse (Q, D, clk, clk_, de, de_, hold, hold_, se, se_, si);
output Q;
input D, clk, clk_, de, de_, hold, hold_, se, se_, si;
supply1 vddA;
supply1 vddR;
supply0 gndR;
not #(0) U45(hnl_141, hnl_68);
not #(0) U31(hnl_68, Q);
latW U28(hnl_58, hnl_54);
latW U30(Q, hnl_269);
cxfr U27(hnl_54, clk_, clk, sh);
cxfr U24(sh, hold, hold_, hnl_141);
cxfr U25(sh, de, de_, D);
cxfr U26(sh, se, se_, si);
cxfr U29(hnl_269, clk, clk_, hnl_58);
endmodule

module w5BIST (BISTFlag, brd_1_, brd_0_, ionbist, iotest, so, BISTMode, IOSTMode, RD_1_, RD_0_, Reset, SynClk, scanM_, se, si_);
output BISTFlag, brd_1_, brd_0_, ionbist, iotest, so;
input BISTMode, IOSTMode, RD_1_, RD_0_, Reset, SynClk, scanM_, se, si_;
supply1 vddA;
supply1 vddR;
supply0 gndR;
vqao21 U64(brd_1_, hnl_105, hnl_270, iotest);
vqmsrse I122(hnl_271, hnl_101, SynClk, hnl_128, cnt84, hnl_83, hnl_14, hnl_272, hnl_99, rstP_, gndR);
vqmsrse I76(hnl_273, hnl_274, SynClk, hnl_128, cnt82, hnl_77, hnl_275, hnl_82, hnl_99, rstP_, gndR);
nand #(0) U63(hnl_105, hnl_42, bit2_, hnl_89, IOSTM_);
nand #(0) U116(hnl_41, hnl_274, hnl_83, hnl_77, hnl_99);
nor #(0) U70(cnt84, hnl_84, IOSTMode, hnl_113);
nor #(0) U88(hnl_101, hnl_276, hnl_277, hnl_145);
nor #(0) U141(brd_0_, brd_1_, iotest);
nor #(0) U138(iotest, bist, IOSTM_);
nor #(0) U20(hnl_92, hnl_227, hnl_67);
nor #(0) U26(hnl_69, hnl_227, hnl_58);
nor #(0) U33(hnl_166, hnl_227, hnl_68);
nor #(0) U61(hnl_89, bit4, bit6);
nor #(0) U60(hnl_42, bit3, bit5);
nor #(0) U62(hnl_278, bit4_, bit6_);
nor #(0) U78(cnt82, hnl_103, hnl_113);
nor #(0) U69(hnl_14, hnl_99, cnt84);
nor #(0) U82(hnl_275, hnl_99, cnt82);
nor #(0) U89(hnl_145, hnl_38, hnl_273);
nor #(0) U86(hnl_274, hnl_78, hnl_279);
nand #(0) U18(hnl_227, bit0, bit1, bit2);
nand #(0) U31(hnl_68, bit3, bit4, bit5);
nand #(0) U68(hnl_84, bit0_, bit1_, bit2);
nand #(0) U67(hnl_103, bit0_, bit1, bit2_);
nand #(0) U50(hnl_125, BISTMode, hnl_74, Reset);
nand #(0) U140(IOSTM_, IOSTMode, Reset);
nand #(0) U142(hnl_270, IOSTMode, bit6_);
nand #(0) U137(ionbist, bist_, IOSTM_);
nand #(0) U14(hnl_280, bit0, bit1);
nand #(0) U28(hnl_58, bit3, bit4);
nand #(0) U66(hnl_113, hnl_42, hnl_278);
nand #(0) U55(rstP_, hnl_281, Reset);
vqmx02 I93(hnl_282, vddR, bit0, bist_, bist);
vqmx02 I94(hnl_283, vddR, hnl_284, bist_, bist);
vqmx02 I95(hnl_285, vddR, hnl_286, bist_, bist);
vqmx02 I96(hnl_287, vddR, hnl_288, bist_, bist);
vqmx02 I97(hnl_289, vddR, hnl_290, bist_, bist);
vqmx02 I98(hnl_291, vddR, hnl_292, bist_, bist);
vqmx02 I99(hnl_293, vddR, hnl_294, bist_, bist);
vqmx02 I129(hnl_284, bit1, bit1_, bit0_, bit0);
vqmx02 I128(hnl_286, bit2, bit2_, hnl_280, hnl_132);
vqmx02 I127(hnl_288, bit3, hnl_67, hnl_227, hnl_63);
vqmx02 I126(hnl_290, bit4, bit4_, hnl_55, hnl_92);
vqmx02 I125(hnl_292, bit5, hnl_56, hnl_65, hnl_69);
vqmx02 I1(hnl_294, bit6, bit6_, hnl_57, hnl_166);
vqmx02 I119(hnl_295, hnl_271, hnl_296, scanM_, hnl_38);
vqmx02 I113(hnl_297, hnl_298, gndR, rstP_, hnl_99);
vqmx02 I112(hnl_298, cnt84, hnl_125, bist, bist_);
vqmsrs I117(hnl_296, hnl_41, hnl_128, SynClk, se, se_, bit6);
vqmsrs I8(bit0, hnl_282, hnl_128, SynClk, se, se_, hnl_299);
vqmsrs I41(bit1, hnl_283, hnl_128, SynClk, se, se_, bit0);
vqmsrs I40(bit2, hnl_285, hnl_128, SynClk, se, se_, bit1);
vqmsrs I39(bit3, hnl_287, hnl_128, SynClk, se, se_, bit2);
vqmsrs I38(bit4, hnl_289, hnl_128, SynClk, se, se_, bit3);
vqmsrs I37(bit5, hnl_291, hnl_128, SynClk, se, se_, bit4);
vqmsrs I35(bit6, hnl_293, hnl_128, SynClk, se, se_, bit5);
vqmsrs I91(hnl_299, BISTMode, hnl_128, SynClk, se, se_, bist);
vqmsrs BM(hnl_300, hnl_88, hnl_128, SynClk, se, se_, hnl_301);
not #(0) U136(so, hnl_302);
not #(0) U135(hnl_302, hnl_296);
not #(0) U134(hnl_301, si_);
not #(0) U133(hnl_279, hnl_303);
not #(0) U132(hnl_303, RD_0_);
not #(0) U131(hnl_277, hnl_304);
not #(0) U130(hnl_304, RD_1_);
not #(0) U121(BISTFlag, hnl_295);
not #(0) U109(se_, se);
not #(0) U44(hnl_128, SynClk);
not #(0) U30(bit6_, bit6);
not #(0) U24(hnl_56, bit5);
not #(0) U22(bit4_, bit4);
not #(0) U16(hnl_67, bit3);
not #(0) U12(bit2_, bit2);
not #(0) U9(bit0_, bit0);
not #(0) U11(bit1_, bit1);
not #(0) U15(hnl_132, hnl_280);
not #(0) U19(hnl_63, hnl_227);
not #(0) U34(hnl_57, hnl_166);
not #(0) U27(hnl_65, hnl_69);
not #(0) U23(hnl_55, hnl_92);
not #(0) U81(hnl_83, cnt84);
not #(0) U80(hnl_77, cnt82);
not #(0) U79(hnl_272, hnl_14);
not #(0) U83(hnl_82, hnl_275);
not #(0) U87(hnl_276, hnl_279);
not #(0) U85(hnl_78, hnl_277);
not #(0) U120(hnl_38, scanM_);
not #(0) U56(hnl_99, rstP_);
not #(0) U114(hnl_88, hnl_297);
not #(0) U57(hnl_281, BISTMode);
not #(0) U92(hnl_74, hnl_299);
not #(0) U49(bist_, hnl_300);
not #(0) U123(bist, bist_);
endmodule

module rac(RData7, RData6, RData5, RData4, RData3, RData2, RData1, RData0,
 SynClk, SynClkFd,
 SOut, BusEnable, SInI, BISTFlag, SCANOut,
 BusCtrl, BusData,
 BusClk, BDSel, BCSel, BESel, RDSel, RCSel,
 Reset,
 TData7, TData6, TData5, TData4, TData3, TData2, TData1, TData0,
 SIn, SOutI, Vref,
 BISTMode, IOSTMode, SCANMode, SCANClk, SCANEn, SCANIn, SynClkIn,
 CCtlEn, CCtlLd, CCtlI, CCtlPgm, PwrUp, ExtBE, StopR, StopT,
 ByPass, ByPSel, rclkASIC, tclkASIC, PhStall);
 
output  [9:0]   RData7, RData6, RData5, RData4, RData3, RData2, RData1, RData0;
output          SynClk, SynClkFd;
output          SOut, BusEnable, SInI;
output          BISTFlag, SCANOut;
 
inout           BusCtrl;
inout   [8:0]   BusData;
input           BusClk;
input   [3:0]   BDSel, BCSel, BESel, RDSel, RCSel;
input           Reset;
input   [10:0]  TData7, TData6, TData5, TData4, TData3, TData2, TData1, TData0;
input           SIn, SOutI, Vref;
input           BISTMode, IOSTMode, SCANMode, SCANClk, SCANEn, SCANIn, SynClkIn;
input           CCtlEn, CCtlLd;
input   [5:0]   CCtlI;
input           CCtlPgm, PwrUp, ExtBE, StopR, StopT;
input           ByPass, ByPSel, rclkASIC, tclkASIC, PhStall;
 
wire          ReqEn;
wire          ASynIn, ASynOut, Transmit;
wire  [5:0]   CCtlO;
supply1 vddA;
supply1 vddR;
supply0 gndR;

w5RACR RR(BusEnable, RData7[8], RData6[8], RData5[8], RData4[8], RData3[8], RData2[8], RData1[8], RData0[8], RData7[7], RData6[7], RData5[7], RData4[7], RData3[7], RData2[7], RData1[7], RData0[7],
RData7[6], RData6[6], RData5[6], RData4[6], RData3[6], RData2[6], RData1[6], RData0[6], RData7[5], RData6[5], RData5[5], RData4[5], RData3[5], RData2[5], RData1[5], RData0[5], hnl_313, hnl_314,
hnl_315, hnl_316, BusData[8], BusData[7], BusData[6], BusData[5], ExtBE, Vref, hnl_317, TData7[10], TData6[10], TData5[10], TData4[10], TData3[10], TData2[10], TData1[10], TData0[10], CCtlO[5], CCtlO[4],
CCtlO[3], CCtlO[2], CCtlO[1], CCtlO[0], hnl_318, hnl_319, hnl_320, hnl_321, hnl_322, hnl_323, hnl_324, hnl_325, hnl_326, SCANIn, hnl_327, hnl_328, hnl_329, TData7[8], TData6[8], TData5[8], TData4[8],
TData3[8], TData2[8], TData1[8], TData0[8], TData7[7], TData6[7], TData5[7], TData4[7], TData3[7], TData2[7], TData1[7], TData0[7], TData7[6], TData6[6], TData5[6], TData4[6], TData3[6], TData2[6],
TData1[6], TData0[6], TData7[5], TData6[5], TData5[5], TData4[5], TData3[5], TData2[5], TData1[5], TData0[5]);

w5RACL RL(ReqEn, SInI, SOut, Transmit, RData7[9], RData6[9], RData5[9], RData4[9], RData3[9], RData2[9], RData1[9], RData0[9], hnl_330, RData7[4], RData6[4], RData5[4], RData4[4], RData3[4],
RData2[4], RData1[4], RData0[4], RData7[3], RData6[3], RData5[3], RData4[3], RData3[3], RData2[3], RData1[3], RData0[3], RData7[2], RData6[2], RData5[2], RData4[2], RData3[2], RData2[2], RData1[2],
RData0[2], RData7[1], RData6[1], RData5[1], RData4[1], RData3[1], RData2[1], RData1[1], RData0[1], RData7[0], RData6[0], RData5[0], RData4[0], RData3[0], RData2[0], RData1[0], RData0[0], hnl_331,
BusCtrl, BusData[4], BusData[3], BusData[2], BusData[1], BusData[0], Reset, SIn, SOutI, hnl_332, Vref, hnl_317, TData7[9], TData6[9], TData5[9], TData4[9], TData3[9], TData2[9], TData1[9], TData0[9],
CCtlO[5], CCtlO[4], CCtlO[3], CCtlO[2], CCtlO[1], CCtlO[0], hnl_333, hnl_334, hnl_318, hnl_320, hnl_321, hnl_335, hnl_322, hnl_323, hnl_324, hnl_325, hnl_336, hnl_315, hnl_316, hnl_329, TData7[4],
TData6[4], TData5[4], TData4[4], TData3[4], TData2[4], TData1[4], TData0[4], TData7[3], TData6[3], TData5[3], TData4[3], TData3[3], TData2[3], TData1[3], TData0[3], TData7[2], TData6[2], TData5[2],
TData4[2], TData3[2], TData2[2], TData1[2], TData0[2], TData7[1], TData6[1], TData5[1], TData4[1], TData3[1], TData2[1], TData1[1], TData0[1], TData7[0], TData6[0], TData5[0], TData4[0], TData3[0],
TData2[0], TData1[0], TData0[0]);

w5RACC RC(hnl_323, SynClk, SynClkFd, hnl_332, hnl_337, hnl_338, hnl_334, hnl_318, hnl_319, hnl_320, hnl_321, hnl_335, hnl_322, hnl_324, hnl_325, hnl_339, hnl_336, hnl_329, BCSel[3], BCSel[2],
BCSel[1], BCSel[0], BDSel[3], BDSel[2], BDSel[1], BDSel[0], BESel[3], BESel[2], BESel[1], BESel[0], BusClk, ByPSel, ByPass, CCtlLd, PhStall, PwrUp, RCSel[3], RCSel[2], RCSel[1], RCSel[0], RDSel[3],
RDSel[2], RDSel[1], RDSel[0], Reset, SCANClk, SCANEn, SCANMode, StopR, StopT, SynClkIn, Vref, hnl_317, hnl_330, rclkASIC, hnl_313, tclkASIC);

w5CCtrl CC(CCtlO[5], CCtlO[4], CCtlO[3], CCtlO[2], CCtlO[1], CCtlO[0], hnl_326, CCtlEn, CCtlI[5], CCtlI[4], CCtlI[3], CCtlI[2], CCtlI[1], CCtlI[0], CCtlPgm, hnl_337, Vref, hnl_338, hnl_320, Reset,
hnl_323, hnl_325, hnl_314, hnl_339);

w5BIST BT(BISTFlag, hnl_327, hnl_328, hnl_317, hnl_333, SCANOut, BISTMode, IOSTMode, RData1[0], RData0[0], Reset, hnl_332, hnl_323, hnl_325, hnl_331);

endmodule