/*----------------------------------------------------------------------------
!
!	mrom64m.vnl - 
!
!			COPYRIGHT 1994 BY
!                    Mega Chips Corporation
!
!-----------------------------------------------------------------------------
!
!++
!
! TITLE:		64M Mask ROM
! CATEGORY:		Behavior Mode (for Verilog-XL)
! ENVIRONMENT:		Cadence Verilog-XL v1.6a4, v1.6a7, v1.7
! Author:		@f
! CREATION DATE: 	1994/06/13
! FINAL UPDATE:		94/06/21 18:08:57 v1.10
! VERSION:		v1.10
!
*/

`timescale 1ns / 1ns

module mrom64m (AD, ALEH, ALEL, CEB, RDB);

    // Definition of input/inout/output port
    inout	[15:0] AD;
    input	ALEH, ALEL, CEB, RDB;

    // Definition of Device Dependent Information
    parameter	DECODE_DATA	= 4'b0000 ;
    parameter	MAX_MEM		= 8388608 ;
    parameter	FILE_NAME = "rom_";
    parameter	FILE_EXT = ".data";

    // Internal Register
    reg		[7:0]		mem[0:MAX_MEM-1];
    reg		[15:0]		Data;
    reg		[6:0]		ARegH;
    reg		[15:1]		ARegL;
    reg		[3:0]		DecReg;
    reg				CEflag;		// for syncronous chip-enable
    reg				CDflag;		// for decoded chip-enable

    // Internal pesudo-Register
    reg		[3:0]		mode;

    // Definition of internal pesudo-mode number (Main Sequence)
    parameter	Init		= 0,
		Standby		= 1,
		SetAdrsH	= 2,
		SetAdrsL	= 3,
		DataOut		= 4,
		DoutDisable	= 5,
		Error		= 6;

    // Error Message
    reg		[8*64:1]	ErrMsg;
    reg				error;
    wire			tim_check = (mode != Init && mode != Error);
    wire			tim_check2 = (mode != Init && mode != Standby && mode != Error);

    // Definition of output delay parameter [nS]
    parameter
		tRD = 100,	// RDB Access Time [nS]
		tOH = 0,	// Output Hold Time [nS]
		tDF = 50;	// Output Float Time [nS]

    assign 	AD = Data;

    ////////////////////////////////////////////////////////////////////////
    // Initialize


   initial begin : load_memory
     reg [7:0] file_number;
     reg [19*8-1:0] file_name;

     if ($test$plusargs("load_rom")) begin
       if (DECODE_DATA > 9) file_number = "a" + DECODE_DATA - 10;
       else                 file_number = "0" + DECODE_DATA;

       file_name = {FILE_NAME, file_number, FILE_EXT};

       $display("loading ROM %h from %s...", DECODE_DATA[3:0], file_name);
       $readmemh(file_name, mem);
       end
     end


    initial begin

	// Initialize Internal Register
	mode = Init;

	// Initialize Data Output Register
	Data = 'bz;
    end


    ////////////////////////////////////////////////////////////////////////
    // ALEH ~\_ Action
    always @(negedge ALEH) begin : negedgeALEH
	reg	[3:0]	Mode;

	Mode = mode;
	case (Mode)
	    Standby:
		begin
		    casex ({ALEL,RDB})
			2'bx0:
				begin
					ErrMsg = "negedge ALEH (RDB!=1)";
					ErrorAction;
				end
			2'b01:
				begin
					ErrMsg = "negedge ALEH (ALEL!=1)";
					ErrorAction;
				end
			2'b11:	SetAdrsHAction;
		    endcase
		end
	    SetAdrsH: ;		// none
	    SetAdrsL: ;		// none
	    DataOut: ;		// none
	    DoutDisable: ;	// none
	    Error: ;		// continue
	endcase
    end

    ////////////////////////////////////////////////////////////////////////
    // ALEH _/~ Action
    always @(posedge ALEH) begin : posedgeALEH
	reg	[3:0]	Mode;

	Mode = mode;
	case (Mode)
    	    Init:
		begin
			if (RDB == 1) StandbyAction;
			else begin
				ErrMsg = "posedge ALEH (RDB!=1)";
				ErrorAction;
			end
		end
	    Standby: ;		// continue
	    SetAdrsH:		StandbyAction;
	    SetAdrsL: 		StandbyAction;
	    DataOut:
		begin
			if (RDB == 1)	StandbyAction;
			else begin
				ErrMsg = "posedge ALEH (RDB!=1)";
				ErrorDisplay;
				StandbyAction;
			end
		end
	    DoutDisable:	StandbyAction ;
	    Error:		if (RDB == 1) StandbyAction;
	endcase
    end

    ////////////////////////////////////////////////////////////////////////
    // ALEL ~\_ Action
    always @(negedge ALEL) begin : negedgeALEL
	reg	[3:0]	Mode;

	Mode = mode;
	case (Mode)
    	    Init:
		begin
			ErrMsg = "negedge ALEL (Initial)";
			ErrorAction;
		end
	    Standby:
		begin
			if (CEflag!==0 && CDflag!==0) begin
				ErrMsg = "negedge ALEL (not Latch AdrsH)";
				ErrorAction;
			end else
				StandbyAction;
		end
	    SetAdrsH:
		begin
			if (CEflag==1 && CDflag==1)	SetAdrsLAction;
			else				StandbyAction;
		end
	    SetAdrsL: 	;	// none
	    DataOut:	;	// none
	    DoutDisable: ;	// none
	    Error:	;	// continue
	endcase
    end

    ////////////////////////////////////////////////////////////////////////
    // ALEL _/~ Action
    always @(posedge ALEL) begin : posedgeALEL
	reg	[3:0]	Mode;

	Mode = mode;
	case (Mode)
    	    Init:
		begin
			if (RDB == 1)	StandbyAction;
			else begin
				ErrMsg = "posedge ALEL (Initial)";
				ErrorAction;
			end
		end
	    Standby:		;	// continue
	    SetAdrsH:		if (!(CEflag==1 && CDflag==1))	StandbyAction;
	    SetAdrsL: 		StandbyAction;
	    DataOut:
		begin
			if (RDB == 1)	StandbyAction;
			else begin
				ErrMsg = "posedge ALEL (RDB!=1)";
				ErrorDisplay;
				StandbyAction;
			end
		end
	    DoutDisable: 	StandbyAction;
	    Error:		if (RDB == 1) StandbyAction;
	endcase
    end

    ////////////////////////////////////////////////////////////////////////
    // RD ~\_ Action
    always @(negedge RDB) begin : negedgeRDB
	reg	[3:0]	Mode;

	Mode = mode;
	case (Mode)
    	    Init:
		begin
			ErrMsg = "negedge RDB (Initial)";
			ErrorAction;
		end
	    Standby:
		begin
			if (CEflag==1 && CDflag==1) begin
				ErrMsg = "negedge RDB (not Latch AdrsH,L)";
				ErrorAction;
			end
		end
	    SetAdrsH:
		begin
			if (CEflag==1 && CDflag==1) begin
				ErrMsg = "negedge RDB (not Latch AdrsL)";
				ErrorAction;
			end else	StandbyAction;
		end
	    SetAdrsL:		DataOutAction;
	    DataOut:		;	// none
	    DoutDisable:	DataOutAction;
	    Error:
		begin
			ErrMsg = "negedge RDB (not Latch AdrsH,L)";
			ErrorAction;
			DataOutAction;
		end
	endcase

    end

    ////////////////////////////////////////////////////////////////////////
    // RD _/~ Action
    always @(posedge RDB) begin : posedgeRDB
	reg	[3:0]	Mode;

	Mode = mode;
	case (Mode)
    	    Init:
		begin
			ErrMsg = "posedge RDB (Initial)";
			ErrorAction;
		end
	    Standby:
		if (CEflag==1 && CDflag==1) begin
			ErrMsg = 0;
			ErrorAction;
		end
	    SetAdrsH:		;	// none
	    SetAdrsL:		;	// none
	    DataOut:		DoutDisableAction;
	    DoutDisable:	;	// none
	    Error:		DoutDisableAction;
	endcase
    end

    ////////////////////////////////////////////////////////////////////////
    // Timing Error Handler
    ////////////////////////////////////////////////////////////////////////
    always @error begin
	if (mode != Standby) begin
		ErrMsg = 0;
		ErrorAction;
	end
    end


    //----------------------------------------------------------------------
    // ErrorAction
    //----------------------------------------------------------------------
    task ErrorAction ;
	begin
		if ($time && (ErrMsg != 0)) begin
			$display("ERROR 64M MROM at %0s : %t",
				ErrMsg, $time);
		end
		mode = Error;
		{ARegH,ARegL} = 'bx;
		CEflag = 'bx;
		CDflag = 'bx;
	end
    endtask


    //----------------------------------------------------------------------
    // ErrorDisplay
    //----------------------------------------------------------------------
    task ErrorDisplay ;
	begin
		if ($time && (ErrMsg != 0)) begin
			$display("ERROR 64M MROM at %0s : %t",
				ErrMsg, $time);
		end
	end
    endtask


    //----------------------------------------------------------------------
    // StandbyAction
    //----------------------------------------------------------------------
    task StandbyAction ;
    	begin
		case (mode)
		    DataOut:		disable DataOutAction;
		    DoutDisable:	disable DoutDisableAction;
		endcase
		mode = Standby;
		{ARegH,ARegL} = 'bx;
		Data = 'bz;
    	end
    endtask


    //----------------------------------------------------------------------
    // SetAdrsHAction
    //----------------------------------------------------------------------
    task SetAdrsHAction ;
	begin
		// Get AddressH / Decode Data
		ARegH = {AD[6],AD[5],AD[4],AD[3],AD[2],AD[1],AD[0]};
		DecReg = {AD[12],AD[11],AD[8],AD[7]};

		// Set Mode
		mode = SetAdrsH;

		// Check Decode Address
		if (DecReg == DECODE_DATA)	CDflag = 1;
		else				CDflag = 0;

		// Check CEB
		if (CEB == 0)			CEflag = 1;
		else				CEflag = 0;
	end
    endtask


    //----------------------------------------------------------------------
    // SetAdrsLAction
    //----------------------------------------------------------------------
    task SetAdrsLAction ;
	begin
		mode = SetAdrsL;
		ARegL = {AD[15],AD[14],AD[13],AD[12],AD[11],AD[10],AD[9],AD[8],AD[7],AD[6],AD[5],AD[4],AD[3],AD[2],AD[1]};
	end
    endtask


    //----------------------------------------------------------------------
    // DataOutAction
    //----------------------------------------------------------------------
    task DataOutAction ;
	begin
		disable posedgeRDB;
		// Data Output
		mode = DataOut;
		if (!(CEflag===0 || CDflag===0)) begin
			Data = 'bx;
			fork
				#tRD Data[15:8] = mem[{ARegH,ARegL,1'b1}];
				#tRD Data[ 7:0] = mem[{ARegH,ARegL,1'b0}];
			join
		end else begin
			Data = 'bz;
		end
	end
    endtask


    //----------------------------------------------------------------------
    // DoutDisableAction
    //----------------------------------------------------------------------
    task DoutDisableAction ;
	begin
		disable negedgeRDB;
		mode = DoutDisable;

		if (ALEH==0 && ALEL==0 && !(CEflag===0 || CDflag===0)) begin
			// Output Disable Data
			#tOH		Data = 'bx;

			// Floating Data
			#(tDF-tOH)	Data = 'bz;

			// Increment Address Counter
			ARegL[8:1] = ARegL[8:1] + 1;
		end else begin
			Data = 'bz;
		end
	end
    endtask


    ////////////////////////////////////////////////////////////////////////
    // Timing Check
    ////////////////////////////////////////////////////////////////////////
    specify
	specparam
			tALLS = 50,	// ALEL Setup Time [nS]
			tALEW = 50,	// ALEH/ALEL Pulse Width [nS]
			tALED = 50,	// ALEH/ALEL Delay Time [nS]
			tAS = 30,	// Address Setup Time [nS]
			tAH = 0,	// Address Hold Time [nS]
			tCES = 20,	// CEB Setup Time [nS]
			tCEH = 0,	// CEB Hold Time [nS]
			tL = 2000,	// Read Latency Time [nS]
			tCYC = 400,	// Read Cycle Time [nS]
			tRDH = 20,	// RDB High Time [nS]
			tRDL = 20;	// RDB Low Time [nS]

	// ALEH ~\_ -> ADxx : Setup & Hold Time check
	$setuphold(negedge ALEH, AD[12], tAS, tAH, error);
	$setuphold(negedge ALEH, AD[11], tAS, tAH, error);
	$setuphold(negedge ALEH, AD[8], tAS, tAH, error);
	$setuphold(negedge ALEH, AD[7], tAS, tAH, error);
	$setuphold(negedge ALEH, AD[6], tAS, tAH, error);
	$setuphold(negedge ALEH, AD[5], tAS, tAH, error);
	$setuphold(negedge ALEH, AD[4], tAS, tAH, error);
	$setuphold(negedge ALEH, AD[3], tAS, tAH, error);
	$setuphold(negedge ALEH, AD[2], tAS, tAH, error);
	$setuphold(negedge ALEH, AD[1], tAS, tAH, error);
	$setuphold(negedge ALEH, AD[0], tAS, tAH, error);

	// ALEL ~\_ -> ADxx : Setup & Hold Time check
	$setuphold(negedge ALEL, AD[15], tAS, tAH, error);
	$setuphold(negedge ALEL, AD[14], tAS, tAH, error);
	$setuphold(negedge ALEL, AD[13], tAS, tAH, error);
	$setuphold(negedge ALEL, AD[12], tAS, tAH, error);
	$setuphold(negedge ALEL, AD[11], tAS, tAH, error);
	$setuphold(negedge ALEL, AD[10], tAS, tAH, error);
	$setuphold(negedge ALEL, AD[9] , tAS, tAH, error);
	$setuphold(negedge ALEL, AD[8] , tAS, tAH, error);
	$setuphold(negedge ALEL, AD[7] , tAS, tAH, error);
	$setuphold(negedge ALEL, AD[6] , tAS, tAH, error);
	$setuphold(negedge ALEL, AD[5] , tAS, tAH, error);
	$setuphold(negedge ALEL, AD[4] , tAS, tAH, error);
	$setuphold(negedge ALEL, AD[3] , tAS, tAH, error);
	$setuphold(negedge ALEL, AD[2] , tAS, tAH, error);
	$setuphold(negedge ALEL, AD[1] , tAS, tAH, error);

	// ALEH ~\_ -> CEB : Setup & Hold Time check
	$setuphold(negedge ALEH, CEB, tCES, tCEH, error);

	// ALEL/ALEH width check
	$width(posedge ALEH &&& tim_check, tALEW, 0, error);
	$width(negedge ALEH &&& tim_check, tALEW, 0, error);
	$width(posedge ALEL &&& tim_check, tALEW, 0, error);
	$width(negedge ALEL &&& tim_check, tALEW, 0, error);

	// RDB ~\_/~\_ cycle check
	$period(negedge RDB &&& tim_check2, tCYC, error);

	// RDB _/~\_ width check
	$width(posedge RDB &&& tim_check2, tRDH, 0, error);

	// RDB ~\_/~ width check
	$width(negedge RDB &&& tim_check2, tRDL, 0, error);

	// ALEL ~\_ -> RDB ~\_ : width check
	$recovery(negedge ALEL &&& tim_check, negedge RDB &&& tim_check2, tL, error);

	// ALEL _/~ -> ALEH ~\_ : width check
	$recovery(posedge ALEL &&& tim_check, negedge ALEH &&& tim_check, tALLS, error);

	// ALEH ~\_ -> ALEL ~\_ : width check
	$recovery(negedge ALEH &&& tim_check, negedge ALEL &&& tim_check, tALED, error);
    endspecify

endmodule