/************************************************************************\
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 \************************************************************************/

// $Id: rwrom.v,v 1.1.1.1 2002/05/17 06:14:57 blythe Exp $
// SCCSID: %W% %G%

`timescale 1ns / 1ns

/************************************************************************
  RWROM - A readable/writable ROM (I known, contradictory in terms) for
  testing the PI Controller.
 ************************************************************************/

module rwrom (AD, ALEH, ALEL, WRB, RDB);

  inout [15:0] AD;                      // AD16 tri-state bus
  input ALEH;                           // high address latch enable
  input ALEL;                           // low  address latch enable
  input WRB;                            // write enable bar
  input RDB;                            // read  enable bar

  `include "define.vh"

  parameter ADDR_KEY   = 4'b0000;       // Address[28:27,24:23]
  parameter PAGE_SIZE  = 4'h3;          // 2^(PAGE_SIZE+1) 16b words
  parameter RWROM_SIZE = 'h80_0000;     // memory size (8MB)

  parameter tRD = 100;                  // read access time
  parameter tOH =   0;                  // read output hold time

  reg   [15:0]  mem[0:RWROM_SIZE-1];    // memory
  reg   [15:0]  ad_out;
  reg   [31:1]  address;                // paging not emulated
  reg           select;                 // address space decode

  integer       rom_dump;               // handle for output file

  initial begin
    if ($test$plusargs("unload_rom")) begin
        rom_dump = $fopen("rom.dump");
        if (rom_dump == 0)
            $display("Error: RWROM - cannot open rom.dump!");
    end
  end

  assign AD = ad_out;

  //        _
  // ALEH:   \_
  //
  initial begin
    #4;	// avoid giving spurious error messages during reset
    forever @(negedge ALEH) begin
      if (ALEL == 1'b0)
        $display("Error: RWROM - negedge ALEH while ALEL is low");
      address[31:16] <= { 9'b0, AD[6:0] };
      casex( { AD[12:11], AD[8:7] } )
        ADDR_KEY: select <= 1'b1;
        default:  select <= 1'b0;
      endcase
    end
  end

  //        _
  // ALEL:   \_
  //
  initial begin
    #4;	// avoid giving spurious error messages during reset
    forever @(negedge ALEL) begin
      if (ALEH == 1'b1)
        $display("Error: RWROM - negedge ALEL while ALEH is high");
      address[15:1] <= AD[15:1];
    end
  end

  //      _     _
  // RDB:  \___/
  //
  always @(RDB) begin
    if ((RDB == 1'b0) & (select == 1'b1))
        ad_out <= #tRD mem[address];
    else
        ad_out <= #tOH 16'hzzzz;
  end

  //      _     _
  // WRB:  \___/
  //
  always @(WRB or AD) begin
    if ((WRB == 1'b0) & (select == 1'b1)) begin
        mem[address[31:1]] <= AD;
        if (rom_dump != 0)
            $fwrite(rom_dump,"@%h: %h\n", {address[31:1],1'b0}, AD);
    end
  end

  always @(posedge WRB or posedge RDB) begin
    address[PAGE_SIZE+1:1] <= address[PAGE_SIZE+1:1]+1;
  end

  //
  // INVALID SIGNAL COMBINATION CHECK
  //
  initial begin
    #4;	// avoid giving spurious error messages during reset
      if (((ALEH | ALEL) & (!RDB | !WRB)) | (!RDB & !WRB))
        $display("Error: RWROM - Invalid signal combination: ALEH=%d ALEL=%d RDB=%d WRB=%d",
                 ALEH, ALEL, RDB, WRB);
    wait(`SYSTEM_READY);
    forever @(ALEH or ALEL or RDB or WRB) begin
      if (((ALEH | ALEL) & (!RDB | !WRB)) | (!RDB & !WRB))
        $display("Error: RWROM - Invalid signal combination: ALEH=%d ALEL=%d RDB=%d WRB=%d",
                 ALEH, ALEL, RDB, WRB);
    end
  end

  //
  // Timing behavior: unit = [ns]
  //
  specify

    specparam

        tALES =   50,                   // ALEL setup time
        tALED =   50,                   // ALEL delay time
        tAS   =   30,                   // Address setup time
        tAH   =    0,                   // Address hold time
        tL    = 2000,                   // Read/write latency time
        tP    =   20,                   // RDB,WRB pulse width
        tR    =   20,                   // RDB,WRB release time

        tRCYC =  400,                   // Read cycle time
        tDF   =   70,                   // Read output disable time
        tRRC  =    0,                   // Read recovery time
        tRSD  =    0,                   // Read start delay time

        tWCYC =  400,                   // Write cycle time
        tDS   =   20,                   // Write data setup time
        tDH   =    0,                   // Write data hold time
        tWRC  =   20,                   // Write recovery time
        tWSD  =    0;                   // Write start delay time

    $recovery(posedge ALEL, negedge ALEH, tALES);
    $recovery(negedge ALEH, negedge ALEL, tALED);
    $setuphold(negedge ALEH, AD, tAS, tAH);
    $setuphold(negedge ALEL, AD, tAS, tAH);

    $recovery(negedge ALEL, negedge RDB, tL);
    $width(negedge RDB, tP);
    $width(posedge RDB, tR);
    $period(negedge RDB, tRCYC);

    $recovery(negedge ALEL, negedge WRB, tL);
    $width(negedge WRB, tP);
    $width(posedge WRB, tR);
    $period(negedge WRB, tWCYC);
    $recovery(posedge WRB, posedge ALEH, tWRC);
    $recovery(posedge WRB, posedge ALEL, tWRC);

  endspecify

endmodule


/************************************************************************
    Prefix Notation:
        First Char      Second Char     Third Char
        --------------  --------------  -------------
        i = input       c = control     r = register
        o = output      s = signal      w = wire
        l = local       d = data        m = memory
        t = tri-state   a = address
                        b = bus
 ************************************************************************/