io_mem_dma.ss
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/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = "io_mem_dma"
wire_load = 256000
standard_load = 0.01
clock = "clock"
default_input_delay = 1.5
default_output_delay = 13.0
default_pin_delay = 10.0
default_input_load = 20
default_output_load = 20
default_pin_load = 150
default_drive_cell = "dfntnh"
default_drive_pin = "q"
default_period = 16.0
default_max_transition = 2.0
default_uncertainty = 1.0
/*****************************************************************************/
/* set the path and read */
/*****************************************************************************/
search_path = {. \
/ecad/synopsys/current/libraries/syn \
/ecad/reality/lib/synopsys/nec35_v2.1 \
/ecad/reality/lib/synopsys/rcp_lib};
search_path = search_path \
+ "../src" \
+ "../../inc" \
+ "../../../lib/verilog/user" \
+ "../../syn"
read -f verilog cbus_driver.v
read -f verilog cp0_driver.v
read -f verilog module + ".v"
current_design mem_dma
/*****************************************************************************/
/* default environment */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/*****************************************************************************/
/* clock constraints */
/*****************************************************************************/
create_clock clock -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -propagated -uncertainty default_uncertainty clock
set_dont_touch_network clock
/*****************************************************************************/
/* default constraint */
/*****************************************************************************/
set_max_area 0
set_dont_touch { ne35hd130d/nt01d* }
/*
set_dont_touch { ne35hd130d/ni01d* }
set_dont_touch find (net, cp0_data)
set_dont_touch find (net, cbus_data)
*/
set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null
set_drive 0 { clock }
set_input_delay 0 { clock }
set_max_transition default_max_transition current_design
/*****************************************************************************/
/* custom constraints */
/*****************************************************************************/
set_driving_cell -cell ni01d5 { *_read_enable *_write_enable }
set_input_delay 5.0 -clock clock { cbus_read_enable }
set_input_delay 5.0 -clock clock { cbus_write_enable }
set_driving_cell -cell nt01d5 { cbus_data_in }
set_load 200 * standard_load { cbus_data_in }
set_load 200 * standard_load { cbus_data }
set_input_delay 10.0 -clock clock { cbus_data_in }
set_output_delay 6.0 -clock clock { cbus_data }
set_driving_cell -cell ni01d5 { dma_start dma_last }
set_load 100 * standard_load { dma_start dma_last }
set_max_fanout 2 * standard_load { dma_start dma_last }
set_driving_cell -cell ni01d5 { cbus_command cbus_select }
set_load 100 * standard_load { cbus_command cbus_select }
set_max_fanout 2 * standard_load { cbus_command cbus_select }
set_input_delay 12.0 -clock clock { set_broke }
set_output_delay 11.0 -clock clock { cmd_ready }
set_output_delay 11.0 -clock clock { io_load }
set_driving_cell -cell nt01d3 { cp0_data_in }
set_input_delay 9.0 -clock clock { cp0_data_in }
set_output_delay 7.0 -clock clock { cp0_data }
set_load 70 * standard_load { cp0_data }
set_load 70 * standard_load { cp0_data_in }
set_output_delay 11.0 -clock clock \
{ pc_data io_write_select interrupt dma_request mem_read \
mem_write }
set_load 150 * standard_load \
{ pc_write pc_data io_write_select halt interrupt dma_request mem_read \
mem_write }
set_input_delay 6.0 -clock clock { cp0_enable }
set_input_delay 3.5 -clock clock { bist_done }
set_input_delay 3.5 -clock clock { bist_fail }
set_output_delay 13.0 -clock clock { halt }
set_output_delay 13.5 -clock clock { pc_write }
set_input_delay 3.0 -clock clock { cmd_address }
set_input_delay 3.0 -clock clock { cmd_read }
set_input_delay 2.0 -clock clock { cp0_address }
set_input_delay 2.0 -clock clock { cp0_cmd_select }
set_input_delay 2.0 -clock clock { cp0_write }
set_output_delay 13.5 -clock clock { mem_address }
/* set_false_path -from reset_l */
set_max_fanout 2 * standard_load reset_l
group_path -name su -weight 100 -critical_range 10000 -from { set_broke, dma_grant }
/*****************************************************************************/
/* check */
/*****************************************************************************/
link
check_design > module + ".lint"
/*****************************************************************************/
/* compile */
/*****************************************************************************/
current_design = mem_dma
ungroup -flatten -all
compile -map_effort high
ungroup -flatten -all
compile -map_effort high
current_design = io_mem_dma
ungroup -flatten -all
/*****************************************************************************/
/* default environment */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/*****************************************************************************/
/* clock constraints */
/*****************************************************************************/
create_clock clock -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -propagated -uncertainty default_uncertainty clock
set_dont_touch_network clock
/*****************************************************************************/
/* default constraint */
/*****************************************************************************/
set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null
set_drive 0 { clock }
set_input_delay 0 { clock }
set_max_transition default_max_transition current_design
/*****************************************************************************/
/* custom constraints */
/*****************************************************************************/
set_driving_cell -cell ni01d5 { *_read_enable *_write_enable }
set_input_delay 5.0 -clock clock { cbus_read_enable }
set_input_delay 5.0 -clock clock { cbus_write_enable }
set_driving_cell -cell nt01d5 { cbus_data }
set_load 200 * standard_load { cbus_data }
set_input_delay 10.0 -clock clock { cbus_data }
set_output_delay 6.0 -clock clock { cbus_data }
set_driving_cell -cell ni01d5 { dma_start dma_last }
set_load 100 * standard_load { dma_start dma_last }
set_max_fanout 2 * standard_load { dma_start dma_last }
set_driving_cell -cell ni01d5 { cbus_command cbus_select }
set_load 100 * standard_load { cbus_command cbus_select }
set_max_fanout 2 * standard_load { cbus_command cbus_select }
set_input_delay 12.0 -clock clock { set_broke }
set_output_delay 11.0 -clock clock { cmd_ready }
set_output_delay 11.0 -clock clock { io_load }
set_driving_cell -cell nt01d3 { cp0_data }
set_input_delay 9.0 -clock clock { cp0_data }
set_output_delay 7.0 -clock clock { cp0_data }
set_load 70 * standard_load { cp0_data }
set_output_delay 11.0 -clock clock \
{ pc_data io_write_select interrupt dma_request mem_read \
mem_write }
set_load 150 * standard_load \
{ pc_write pc_data io_write_select halt interrupt dma_request mem_read \
mem_write }
set_input_delay 6.0 -clock clock { cp0_enable }
set_input_delay 3.5 -clock clock { bist_done }
set_input_delay 3.5 -clock clock { bist_fail }
set_output_delay 13.0 -clock clock { halt }
set_output_delay 13.5 -clock clock { pc_write }
set_input_delay 3.0 -clock clock { cmd_address }
set_input_delay 3.0 -clock clock { cmd_read }
set_input_delay 2.0 -clock clock { cp0_address }
set_input_delay 2.0 -clock clock { cp0_cmd_select }
set_input_delay 2.0 -clock clock { cp0_write }
set_output_delay 13.5 -clock clock { mem_address }
/* set_false_path -from reset_l */
set_max_fanout 2 * standard_load reset_l
group_path -name su -weight 100 -critical_range 10000 -from { set_broke, dma_grant }
/*****************************************************************************/
/* write */
/*****************************************************************************/
include "report.dc"
write -format edif -hierarchy -o module + ".edf" module
write -format db -hierarchy -o module + ".db" module
write -format verilog -hierarchy -o module + ".vsyn" module
quit