/************************************************************************\
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 \************************************************************************/

// $Id: ms_sc.v,v 1.1.1.1 2002/05/17 06:14:57 blythe Exp $
//		module span context:  memspan
//	receive span descriptors, convert into byte addresses via attributes,
//	buffer as rdctxt, rmwctxt, wrctxt versions;
//	calculate rdram addresses and lengths per access;
//	provide interlock so that ewpipe startspan waits if necessary for
//	any span processing to be completed (normally no wait);
//	AND for rdctxt to not go ahead on next span until the rmwctxt
//	has copied over the span context (via ewpipe startspan delayed).
//	also prevent wrctxt span context from being clobbered by rmwctxt
//	when next startspan arrives at wrctxt in the case wrctxt not yet
//	finished writing out old span;  
//	the latter case will always cause stall for back2back spans, so
//	add yet another address buffer (dbl buffered in wrctxt) and only
//	stall if both buffers full...
//	release current buffer asap once dma grant received (address deassert).

//	notions:  perclk is # pixels per clock for count usage;
//		csize is color depth per pixel;
//		# bytes per clock is implied by above BUT loadtlut is special;
//			(handle this special case AT rdcrptr);
//mods:  10-31-94 wrdone/wrbusy:  AND resetcreqw with "!zreqw" for z cases;
//			speedup wrbusy ctxt prop via using "nxt wrdone is high" cond;
//		add resetc/zreqw cases to wrctxt loads; fix rbptr increment cases;
//	 11-1-94 replace assigns with always @ statements to fix stallrdctxt bug;
//		add lastonewz, lastonewez notions; separate steprb*ptr cases;
//	11-2-94 disable rbptr update for fillmode;  move rdspace outside clk
//		eliminate intermingling of read/write ptr update (rbptrs)
//		mod 2 cycle timing of valid as per phil's request
//	  todo:  creqw/zreqw valid for loads, etc;  replace by *reqw&wrenwrite*
//	    in control paths;  allow c/zreqw for non-writes;
//		and add new sm paths for resetc/zreqw and non-write cases;
//	11-3 add lastonee for early update of rbcount values, for ptrs.
//		fixed rdspace, converted rbptr's to 4b, init'd r0w8
//		(still may need to adjust ptr as used by spanbuf reg address)
//	11-5  eliminate cnum16, causes deadlocks
//	11-7  add endspant14/fix rbc/zwptr inc for non-write cases (load)
//		added wrbusy to both terms of wrdone calc, fn of buf we's
//	11-8  mod rdenreadc/z for load using z, rbzwptr inc for no writes w/z rd
//		lastonee mod for z only read case, add wrloadmode for rbzwptr
//	11-12 mod rdperclk, pixcount for load_tlut mode
//	11-15 mod rdrbzrptr/rdrbcrptr to capture full 4b value; make copy zwrite
//		add wrcopymode out to ms_si for cwmask select
//		add mumbo jumbo for rdptr inc on write-only ops (exc. fillmode).
//	11-21 add rdptr update for write-only ops, remove hack;
//	11-23 xor rdcxi etc for all rbc/zr/winc calculations...
//	11-29 wrfillcolor, fix base addresses.... 
//	11-30 mod rdramlen to include offset into start address  (fn of xdec)
//		mod stepping of rdc/zxi to include cases of one read/other write
//	12-1 mod rdspace high for rdcopmode & csize16;
//	12-5 add wrrender, wrrender_buf for 4 word write logic usage
//	  and mod:  rbcountc/zw;  wrc/zxi;  lastonewe/lastonewez;
//	12-6 fix typo in rbcountcw; fix lastonee for case of both read;
//		fix case of multiple read planes stepping, and
//		fix lastonee for same;
//	12-7 mod to input startspand2 for stall gen;
//		mod wrzxi inc for non-wrz to happen at fullzwmt11;
//		mod rbzwptr inc to include case of cwrite/nozwrite, do at fullz
//	  undo d2 mod, reset rd*modes; fix wrbusy case;
//	12-12 fix sensitivity lists after jls synopsys run (rdspace, stallnxtwm)
//		also fix multiple drives:  rdload/copy/fill/twophase, wrcxi;
//	12-13 recode wrc/zxi adders for timing synthesis
//		fix rd2rmw, wrc/zxi init;
//	12-15 fix rdspace to be fn of enabled read planes, mask stale cptr on ld
//	  add wrloadmode out to ms_rp.v, mod endspant14 to t12 in rbzwptrinc
//	12-16 mod wrdone to always be zero even for loads, initially;
//		...undo previous mod...
//	12-19 add wrdone always zero, and term to reset for wrloadmode/endspant12;
//	12-22 add outports wrloadmode_buf, wrenreadz_buf for translucency fix;
//	12-23 more translucency fixes:  wrc/zxi increment
//	12-27 create reg "maskrddone" to fix 4K length load bug end condition;
//	12-28 ditto for "*maskdone"--this time for wrctxt done condition;
//	12-29 edit above to be reset within wrcxi loop (for non-z cases).
//	12-29 mega changes for 32b render fix:  znum2 (loadmode znum4, for now);
//		mod cnum* to compensate...
//		also:  optimize for 2cycle mode (!znum2);
//	12-30 convert lastonee to assign statement;
//	12-30 new year's hack:  loads are znum8, rdspace hi if rmwld & validt2;
//			add input validt2;
//	12-30 add jlsmith's synthesis improvements;
//	******warning:  fz1,fz2 have changed/add znum2:  affect rdzxi adders****//			***not fixed yet***
//	1-3 change wrmaskdone to wrmaskdonec/z for test 28 fix;
//		also:  for maskrddone/rdmaskdone use stepcount NOT pixcount;
//		also:  cleanup reset conditions;
//	1-4 fix assigns for state_byte rdc/zxi;  tweak lastonee for mask c/z;
//		add inport test_mode0 to reset rb*ptrs for debug mode;
//		outports stallrdctxtd, stallwrctxtd, rb*ptrd;
//	1-5 fix state_spanlet :  rdloadmode || rdcopymode addend bug;
//	1-10  reset to zero smcwincwr, smzwincwr for synopsys/synth reasons;
//	1-11  fix diagnostic circular buffer pointer reset values;
//		***register lastonee as lastoneed for jlsmith synth chk***
//		also, mod wrc/zxi iterators to use lastonew, lastonewz;
//		versus lastonewe, lastonewez;
//	1-*13* mods for timing/synth
//	5-25  mods for load_tlut bug, to rdspace
//	6-5  edit out underscores


`timescale 1ns/1ns

module ms_sc(clock, gclock, reset_l, stopgclock,
	cycle_type, image_read_en, z_update_en, z_compare_en,
	color_base, color_size, z_base, tex_base, tex_size, load_en,
	color_format, tex_format, ldtlut_en,
	nextspanxi, nextspanxf, nextspancount, nextspanxdec, spanbufmt,
	startspant0, startspant1, startspant7m, startspant12, steprddone,
	steprbcrptr, steprbzrptr, steprbcwptr, steprbzwptr,
	rdramreqcr, rdramreqzr, rdramreqcw, rdramreqzw, creqw, zreqw,
	resetcreqw, resetzreqw, endspant11, fullcwmt11, fullzwmt11,
	startspant8, endspant12, endspant14, fillcolor, validt2,
	test_mode0,

	rdspace, rddone, rdenreadc, rdenreadz, rdcxi, rdzxi, rdxdec,
	rmwenreadc, rmwenreadz, wrfillmode, wrzxi_buf, wrxdec_buf,
	rmwenwritec, rmwenwritez, wrenwritec_buf, wrenwritez_buf, stallrdctxt, 
	stallwrctxt, rdramreq, rdramlen, rdramaddr, rdramdir, rdramrw,
	rdtwophase, rmwtwophase, rdcopymode, rdfillmode, rdloadmode,
	rmwcopymode, rmwfillmode, rmwloadmode, pixcount, wrfillcolor,
	wrcopymode_buf, wrfillmode_buf, rmwrgbmode, rmwloadtlut,
	rdperclk8, rdperclk4, rdperclk2, rmwperclk8, rmwperclk4, rmwperclk2,
	rmwcsize8, rmwcsize16, rmwcsize32, wrcsize8_buf, wrcsize16_buf,
	wrcsize32_buf, wrcxi_buf, wrcxf_buf, rmwcxi, rmwzxi, rmwxdec,
	stepcount, rbzrptr, rbcrptr, rbzwptr, rbcwptr, wrcxi, wrzxi, wrxdec,
	smcwincwr, smzwincwr, spanproc, savezxi, wrcopymode,
	rmwrbcrptr, rdrbzrptr, wrrbcrptr_buf, wrrbzrptr_buf,
	wrloadmode_buf, wrenreadz_buf, stallrdctxtd, stallwrctxtd,
	rbcrptrd, rbzrptrd, rbcwptrd, rbzwptrd,
	spanbufrd, stallnxtwm, wrrender_buf, wrloadmode);

`include "ms.vh"

input clock;
input gclock;                          		// system stallable clock
input reset_l;                           		// system reset
input stopgclock;

//attribute globals
input [1:0] cycle_type;
input image_read_en;
input z_update_en;
input z_compare_en;
input [25:0] color_base;			//base address
input [1:0] color_size;				//size
input [25:0] z_base;				//base address
input [25:0] tex_base;				//base address
input [1:0] tex_size;				//size
input load_en;					//piped from EW/in spanbuf
input [2:0] color_format;			//color rgbmode or not
input [2:0] tex_format;
input ldtlut_en;				//attribute for tlut mode
input startspant8;
input [31:0] fillcolor;


//memspan ASSUMES base addresses [2:0] are always zero
input [19:0] nextspanxi;
input [11:0] nextspanxf;
input [11:0] nextspancount;
input nextspanxdec;				//right major
//the above needs to be received sync'd with each primitive (as for load_en)
//tho we'll latch it for each span to be coherent in simple way with spanbuf
input spanbufmt;				//spanbuf empty, maybe &!push
input startspant0;
input startspant1;
input startspant7m;
input startspant12;
input steprddone;
input steprbcrptr;
input steprbzrptr;
input steprbcwptr;
input steprbzwptr;
input rdramreqcr;
input rdramreqzr;
input rdramreqcw;
input rdramreqzw;
input creqw;					//need for wrbuf/stall
input zreqw;					//need for wrbuf/stall
input resetcreqw, resetzreqw;
input endspant11;
input fullcwmt11;
input fullzwmt11;
input endspant12;
input endspant14;
input validt2;
input test_mode0;

output rdspace;
output rddone;					//rdctxt idle
output rdenreadc;                                //ctxt enrdcolor
output rdenreadz;                                //ctxt enrddepth
output [25:0] rdcxi, rdzxi;
output rdxdec;
output rmwenreadc, rmwenreadz;
output stallrdctxt;				//stall not ready for nextspan
output stallrdctxtd;
output stallwrctxt;				//write ctxt addr buffer full
output stallwrctxtd;
output rdramreq;
output [6:0] rdramlen;
output [25:0] rdramaddr;
output rdramdir;
output rdramrw;
output rdcopymode;
output rmwcopymode;
output wrcopymode_buf;
output rdtwophase;
output rmwtwophase;
output rmwrgbmode;
output rdfillmode;
output rmwfillmode;
output wrfillmode_buf;
output wrfillmode;
output rdloadmode;
output rmwloadmode;
output rmwloadtlut;
output [11:0] stepcount, pixcount;

output [3:0] rbzrptr;
output [3:0] rbcrptr;
output [3:0] rbzwptr;
output [3:0] rbcwptr;
//the following is used by ms_si.v for rotating bytes of writemasks
output [25:0] rmwcxi, wrcxi;
output [25:0] rmwzxi, wrzxi;
output [25:0] wrcxi_buf, wrzxi_buf;
output [11:0] wrcxf_buf;
output rmwxdec, wrxdec, wrxdec_buf;
output rmwenwritec, rmwenwritez;
output wrenwritec_buf, wrenwritez_buf;

output spanproc;
output wrcopymode;

output [3:0] smcwincwr, smzwincwr;
output [3:0] rmwrbcrptr, rdrbzrptr, wrrbcrptr_buf, wrrbzrptr_buf;
output [3:0] rbcrptrd, rbzrptrd, rbcwptrd, rbzwptrd;

output rmwcsize8, rmwcsize16, rmwcsize32;
output wrcsize8_buf, wrcsize16_buf, wrcsize32_buf;
output rdperclk8, rdperclk4, rdperclk2, rmwperclk8, rmwperclk4, rmwperclk2;
output spanbufrd;					//read spanbuf entry
output stallnxtwm;

output [25:0] savezxi;
output [31:0] wrfillcolor;
output wrrender_buf;
output wrloadmode;
output wrloadmode_buf, wrenreadz_buf;

// input/output registers

// internal registers
reg [25:0] rdcxi;
reg [25:0] rdzxi;
reg [11:0] rdcxf;
reg [11:0] rdzxf;
reg rdxdec;
reg [25:0] savecxi;
reg [25:0] savezxi;
reg [11:0] pixcount;
reg [25:0] rmwcxi;
reg [25:0] rmwzxi;
reg [11:0] rmwcxf;
reg [11:0] rmwzxf;
reg rmwxdec;
reg [25:0] wrcxi;
reg [25:0] wrzxi;
reg [11:0] wrcxf;
reg [11:0] wrzxf;
reg wrxdec;
reg [1:0] fc1;
reg [2:0] fz1;
reg [1:0] fc2;
reg [2:0] fz2;
reg rdperclk2;
reg rdperclk4;
reg rdperclk8;
reg rmwperclk2;
reg rmwperclk4;
reg rmwperclk8;
reg cnum4;
reg cnum8;
reg znum4;
reg znum2;
reg znum8;
reg rdcsize8, rdcsize16, rdcsize32;
reg rmwcsize8, rmwcsize16, rmwcsize32;
reg wrcsize8_buf, wrcsize16_buf, wrcsize32_buf;
reg rdfillmode;
reg wrfillmode;
reg wrfillmode_buf;
reg rmwfillmode;
reg rdcopymode;
reg rmwcopymode;
reg wrcopymode_buf;
reg rmwrgbmode;
reg rdrgbmode;
reg rdloadmode;
reg rmwloadmode;
reg rdloadtlut;
reg rmwloadtlut;
reg spanproc;
reg rddone;
reg lastone;
reg wrdone;
reg lastonew;
reg lastonewz;
reg rd2rmw;				//newspan block if not rdctxt => rmwctxt
reg stallrden;
reg [6:0] rbcountcr;
reg [6:0] rbcountzr;
reg [5:0] rbcountcw;
reg [5:0] rbcountzw;
reg [25:0] wrcxi_buf;
reg [25:0] wrzxi_buf;
reg [11:0] wrcxf_buf;
reg [11:0] wrzxf_buf;
reg wrxdec_buf;
reg rdy4span;
reg wrbusy;
reg rdenreadc;
reg rdenreadz;
reg rmwenreadc, rmwenreadz;
reg rdenwritec;
reg rdenwritez;
reg [3:0] rbcrinc;
reg [3:0] rbzrinc;
reg [3:0] rbcwincwr;
reg [3:0] rbzwincwr;
reg [3:0] rbcrptr;
reg [3:0] rbzrptr;
reg [3:0] rbcwptr;
reg [3:0] rbzwptr;
reg rdtwophase, rmwtwophase;
reg [11:0] stepcount;
reg rmwenwritec;
reg rmwenwritez;
reg wrenwritec;
reg wrenwritez;
reg wrenwritec_buf;
reg wrenwritez_buf;
reg wrenreadc_buf;
reg wrenreadz_buf;
reg wrenreadc;
reg wrenreadz;
reg spanbufrd;
reg wrcopymode;

reg [3:0] smcwincwr, smzwincwr;
reg [3:0] rdrbcrptr, rdrbzrptr, rmwrbcrptr, rmwrbzrptr;
reg [3:0] wrrbcrptr_buf, wrrbzrptr_buf;

reg wrloadmode_buf, wrloadmode;

reg enstepread, stepreaddd, stepreadd, stepread;
reg [31:0] wrfillcolor;

reg wrrender, wrrender_buf;
reg maskrddone;
reg rdmaskdone, rmwmaskdone, wrmaskdone_buf, wrmaskdonec, wrmaskdonez;
reg [3:0] rbcrptrd, rbzrptrd, rbcwptrd, rbzwptrd;
reg stallrdctxtd, stallwrctxtd;

reg lastoneed;

//pseudoregisters
reg [6:0] rdramlen;
reg [25:0] rdramaddr;
reg rdramreq;
reg rdramrw;
reg rdramdir;

//wires

wire lastonee;

// READ CONTEXT state machine
reg [3:0] state;
parameter

	state_idle		= 4'h1,
	state_byte		= 4'h2,
	state_spanlet		= 4'h4,
	state_spanlet2		= 4'h8;

assign stallrdctxt = startspant0 && stallrden;
assign stallwrctxt = startspant7m && wrbusy;
assign stallnxtwm = 0;

      reg [25:0] rdcxi_addend0, rdcxi_addend1;
      reg [11:0] rdcxf_addend0, rdcxf_addend1;
      reg [25:0] rdzxi_addend0, rdzxi_addend1;
      reg [11:0] rdzxf_addend0, rdzxf_addend1;
      reg [25:0] wrcxi_addend0, wrcxi_addend1;
      reg [25:0] wrzxi_addend0, wrzxi_addend1;

// synopsys translate_off
`ifdef MSPAN_MON
reg [1:0] idle_arcs;
reg [10:0] spanlet_arcs;
`endif
// synopsys translate_on

//12-27:  added maskrddone to behavior of depth;
//1-4 add to color as well;

assign	lastonee = (((rdenreadc & !rdenreadz) || ((enstepread || stepread ||
	stepreadd || stepreaddd) & rdenwritec & !rdenwritez)) & !maskrddone &
		((rdcxi[11:5] | (cnum8)) ==
                       (rdcxf[11:5] | (cnum8))) ||
		    ((rdenreadz || ((enstepread || stepread || stepreadd ||
		stepreaddd) & rdenwritez)) & !maskrddone &
			((rdzxi[11:4] | {znum8, (znum8 || znum4)}) ==
			(rdzxf[11:4] | {znum8, (znum8 || znum4)} ))));

always @(wrrender or wrcxi or wrzxi or wrxdec) begin
                if (!wrrender) begin
                        wrcxi_addend0 = { wrcxi[25:6],    1'b1,    5'b00000};
                        wrcxi_addend1 = {{20{wrxdec}}, ~wrxdec, {5{wrxdec}}};
                        wrzxi_addend0 = { wrzxi[25:6],    1'b1,    5'b00000};
                        wrzxi_addend1 = {{20{wrxdec}}, ~wrxdec, {5{wrxdec}}};

                end
                else begin
                        wrcxi_addend0 = { wrcxi[25:5],    1'b1,     4'b0000};
                        wrcxi_addend1 = {{21{wrxdec}}, ~wrxdec, {4{wrxdec}}};
                        wrzxi_addend0 = { wrzxi[25:5],    1'b1,     4'b0000};
                        wrzxi_addend1 = {{21{wrxdec}}, ~wrxdec, {4{wrxdec}}};

                end
end

//RDRAM REQUEST LOGIC
//rdram dma request mux to io unit

always @(rdramreqcr or rdramreqzr or rdramreqcw or rdramreqzw or rbcountcr or
	rbcountzr or rbcountcw or rbcountzw or rdcxi or rdzxi or wrcxi or wrzxi or
	rdxdec or wrxdec) begin

	rdramreq <= rdramreqcr || rdramreqzr || rdramreqcw || rdramreqzw;
	rdramrw <= (rdramreqcr || rdramreqzr);
	rdramdir <= (rdramreqcr || rdramreqzr) ? rdxdec : wrxdec;

        if (rdramreqcr) begin
                rdramlen <= (rbcountcr + (rdcxi[2:0] ^ {3{rdxdec}}));
                rdramaddr <= rdcxi;
                end
        else if (rdramreqzr) begin
                rdramlen <= (rbcountzr + (rdzxi[2:0] ^ {3{rdxdec}}));
                rdramaddr <= rdzxi;
                end
        else if (rdramreqcw) begin
                rdramlen <= (rbcountcw + (wrcxi[2:0] ^ {3{wrxdec}}));
                rdramaddr <= wrcxi;
                end
        else begin
                rdramlen <= (rbcountzw + (wrzxi[2:0] ^ {3{wrxdec}}));
                rdramaddr <= wrzxi;
                end
end

//READ SPACE AVAILABLE CALCULATION
//valid whether reads are done or not....

assign rdspace = 
	(rdcopymode & rdcsize16 | rmwloadmode & validt2 & !rmwloadtlut) |
	((!((rbcwptr - rbcrptr) < rbcrinc) || !rdenreadc) &
                  (!((rbzwptr - rbzrptr) < rbzrinc) || !rdenreadz));

//we guarantee that rbcrinc/rbzrinc are >0 always so can have full range
always @(posedge gclock or negedge reset_l) begin
   if (!reset_l) begin
        rmwtwophase <= low;
//the following must be reset so that lastonew is set, allowing 1st span thru
        wrenwritec_buf <= low;
        wrenwritez_buf <= low;
        rmwcxi <= 26'bx;
        rmwzxi <= 26'bx;
        wrcxi_buf <= 26'bx;
        wrzxi_buf <= 26'bx;
        rmwcxf <= 12'bx;
        rmwzxf <= 12'bx;
        rmwxdec<= low;
        wrxdec_buf <= low;
        wrcxf_buf <= 12'bx;
        wrzxf_buf <= 12'bx;
        rmwperclk2 <= low;
        rmwperclk4 <= low;
        rmwperclk8 <= low;
        rmwcsize8 <= high;
        rmwcsize16 <= low;
        rmwcsize32 <= low;
      wrcsize8_buf <= low;
      wrcsize16_buf <= low;
      wrcsize32_buf <= low;
        rmwcopymode <= low;
        wrcopymode_buf <= low;
        rmwloadmode <= low;
        rmwloadtlut <= low;
        wrfillmode_buf <= low;
        rmwfillmode <= low;
        rmwrgbmode <= low;
        rmwenwritec <= low;
        rmwenwritez <= low;
        rmwenreadc <= low;
        rmwenreadz <= low;
        wrenreadc_buf <= low;
        wrenreadz_buf <= low;
	rmwmaskdone <= low;
	wrmaskdone_buf <= low;
                rmwrbcrptr <= 4'bx;
                rmwrbzrptr <= 4'bx;
                wrrbcrptr_buf <= 4'bx;
                wrrbzrptr_buf <= 4'bx;
                wrloadmode_buf <= low;
                wrrender_buf <= low;
// synopsys translate_off
`ifdef MSPAN_MON
	idle_arcs <= 2'b0;
	spanlet_arcs <= 11'b0;
`endif
// synopsys translate_on
  end
  else begin

//MULTIPLE BUFFERED SPAN CONTEXTS

//wrbusy set when 2nd buffer of write address is loaded;  cleared when it is passed onto
//working buffer. must verify there is no issue of RDP pipeline stall here, e.g. need to
//make sure the wrbusy behavior mimics the creqw/zreqw behavior?!

                if (startspant7m & !wrbusy) begin
                        wrcxi_buf <= #1 rmwcxi;
                        wrzxi_buf <= #1 rmwzxi;
                        wrcxf_buf <= #1 rmwcxf;
                        wrzxf_buf <= #1 rmwzxf;
                        wrxdec_buf <= #1 rmwxdec;
                        wrenreadc_buf <= #1 rmwenreadc;
                        wrenreadz_buf <= #1 rmwenreadz;
                        wrenwritec_buf <= #1 rmwenwritec;
                        wrenwritez_buf <= #1 rmwenwritez;
                        wrfillmode_buf <= #1 rmwfillmode;
                        wrcopymode_buf <= #1 rmwcopymode;
                        wrcsize8_buf <= #1 rmwcsize8;
                        wrcsize16_buf <= #1 rmwcsize16;
                        wrcsize32_buf <= #1 rmwcsize32;
			wrrbcrptr_buf <= #1 rmwrbcrptr;
			wrrbzrptr_buf <= #1 rmwrbzrptr;
			wrloadmode_buf <= #1 rmwloadmode;
			wrrender_buf <= #1 !(rmwcopymode || rmwfillmode ||
						rmwloadmode);
			wrmaskdone_buf <= #1 rmwmaskdone;
                end

                if (startspant1) begin
                        rmwcxi <= #1 savecxi;
                        rmwzxi <= #1 savezxi;
                        rmwcxf <= #1 rdcxf;
                        rmwzxf <= #1 rdzxf;
                        rmwxdec <= #1 rdxdec;
                        rmwenreadc <= #1 rdenreadc;
                        rmwenreadz <= #1 rdenreadz;
                        rmwenwritec <= #1 rdenwritec;
                        rmwenwritez <= #1 rdenwritez;
                        rmwfillmode <= #1 rdfillmode;
                        rmwloadmode <= #1 rdloadmode;
                        rmwloadtlut <= #1 rdloadtlut;
                        rmwcopymode <= #1 rdcopymode;
                        rmwcsize8 <= #1 rdcsize8;
                        rmwcsize16 <= #1 rdcsize16;
                        rmwcsize32 <= #1 rdcsize32;
                        rmwperclk8 <= #1 rdperclk8;
                        rmwperclk4 <= #1 rdperclk4;
                        rmwperclk2 <= #1 rdperclk2;
                        rmwrgbmode <= #1 rdrgbmode;
                        rmwrbcrptr <= #1 rdrbcrptr;
                        rmwrbzrptr <= #1 rdrbzrptr;
			rmwtwophase <= #1 rdtwophase;
			rmwmaskdone <= #1 rdmaskdone;
                end
  end
end

always @(posedge clock or negedge reset_l) begin
   if (!reset_l) begin
      // resettable registers
        wrcxi <= 26'h0;
        wrcxf <= 12'h0;
        wrzxi <= 26'bx;
        wrzxf <= 12'bx;
        wrxdec<= low;
        wrcopymode <= low;
        wrfillmode <= low;
        wrenwritec <= low;
        wrenwritez <= low;
	lastone <= low;
	lastonew <= low;
	lastonewz <= low;
	wrdone <= high;
	spanproc <= low;
	rdy4span <= low;
        rd2rmw <= high;
        state <= state_idle;
	rddone <= high;
	stallrden <= high;
	rbcrptr <= 4'h0;
	rbzrptr <= 4'h0;
	rbcwptr <= 4'h8;
	rbzwptr <= 4'h8;
	rdtwophase <= low;
	wrbusy <= low;
	spanbufrd <= low;
	enstepread <= low;
	stepread <= low;
      rbzrinc <= 4'b0;
      rbcrinc <= 4'b0;
	maskrddone <= low;
	rdmaskdone <= low;
	wrmaskdonec <= low;
	wrmaskdonez <= low;

	rdcxi <= 26'bx;
	rdzxi <= 26'bx;
	savecxi <= 26'bx;
	savezxi <= 12'bx;
        rdcxf <= 12'bx;
        rdzxf <= 12'bx;
	rbcountcr <= 7'bx;
	rbcountzr <= 7'bx;
	rbcountcw <= 7'bx;
	rbcountzw <= 7'bx;
	pixcount <= 12'bx;
	rdxdec <= low;
	fc1 <= 2'bx;
	fc2 <= 2'bx;
	fz1 <= 3'bx;
	fz2 <= 3'bx;
	rdperclk2 <= low;
	rdperclk4 <= low;
	rdperclk8 <= low;
	cnum4 <= low;
	cnum8 <= low;
	znum2 <= low;
	znum4 <= low;
	znum8 <= low;
	rdcsize8 <= high;
	rdcsize16 <= low;
	rdcsize32 <= low;
	rdcopymode <= low;
	rdloadmode <= low;
	rdloadtlut <= low;
	rdfillmode <= low;
	rdrgbmode <= low;
	stepcount <= 12'bx;
	rdenwritec <= low;
	rdenwritez <= low;
	rdenreadc <= low;
	rdenreadz <= low;
                rbcwincwr <= 4'bx;
                rbzwincwr <= 4'bx;
                wrenreadc <= low;
                wrenreadz <= low;
                rdrbcrptr <= 4'bx;
                rdrbzrptr <= 4'bx;
                wrloadmode <= low;
                stepreadd <= low;
                stepreaddd <= low;
                wrfillcolor <= 32'bx;
                wrrender <= low;
      smcwincwr <= 4'b0;
      smzwincwr <= 4'b0;
	rbcrptrd <= 4'b0;
	rbzrptrd <= 4'b0;
	rbcwptrd <= 4'b0;
	rbzwptrd <= 4'b0;
	stallrdctxtd <= 'bx;
	stallwrctxtd <= 'bx;
	
	lastoneed <= low;

      // pseudo registers
      end
   else begin : main_block
      /* synopsys
         resource r_rdcxi:
         map_to_module = "DW01_add",
         implementation = "cla",
         ops = "rdcxi";

         resource r_rdcxf:
         map_to_module = "DW01_add",
         implementation = "cla",
         ops = "rdcxf";

         resource r_rdzxi:
         map_to_module = "DW01_add",
         implementation = "cla",
         ops = "rdzxi";

         resource r_rdzxf:
         map_to_module = "DW01_add",
         implementation = "cla",
         ops = "rdzxf";

         resource r_wrcxi:
         map_to_module = "DW01_add",
         implementation = "cla",
         ops = "wrcxi";

         resource r_wrzxi:
         map_to_module = "DW01_add",
         implementation = "cla",
         ops = "wrzxi";
      */


//      reg lastonee;
      reg lastonewe;
      reg lastonewez;

/*
      reg [25:0] rdcxi_addend0, rdcxi_addend1;
      reg [11:0] rdcxf_addend0, rdcxf_addend1;
      reg [25:0] rdzxi_addend0, rdzxi_addend1;
      reg [11:0] rdzxf_addend0, rdzxf_addend1;
      reg [25:0] wrcxi_addend0, wrcxi_addend1;
      reg [25:0] wrzxi_addend0, wrzxi_addend1;
*/

	lastoneed <= lastonee;

      if (!wrrender) begin
         lastonewe = (wrcxi[11:6] == wrcxf[11:6]) & !wrmaskdonec;
         lastonewez = (wrzxi[11:6] == wrzxf[11:6]) & !wrmaskdonez;
      end
      else begin
         lastonewe = (wrcxi[11:5] == wrcxf[11:5]) & !wrmaskdonec;
         lastonewez = (wrzxi[11:5] == wrzxf[11:5]) & !wrmaskdonez;
      end

      rdcxi_addend0 = rdcxi;
      rdcxi_addend1 = 0;
      rdcxf_addend0 = rdcxf;
      rdcxf_addend1 = 0;
      rdzxi_addend0 = rdzxi;
      rdzxi_addend1 = 0;
      rdzxf_addend0 = rdzxf;
      rdzxf_addend1 = 0;

/*
      wrcxi_addend0 = wrcxi;
      wrcxi_addend1 = 0;
      wrzxi_addend0 = wrzxi;
      wrzxi_addend1 = 0;
*/

       	if (startspant1 & !stopgclock) begin
                rd2rmw <= #1 high;
	end


//RDRAM POINTERS INTO SPANBUF (READ, WRITE C,Z)
//rdram read/write pointers view memory as two 8-word, 144b wide areas c/z
//	msb of ptr address is implied 1 for z, implied 0 for c;
//if no z reads or writes, the z pointers rbzrptr/rbzwptr are static;
//else they behave similarly to c pointers, sortof;
	
//initial cut:  if no reads, the writes will update ptrs.  probably
//unacceptable as will not reliably generate rddone as needed.  a
//different but related issue for no writes case, updating wrdone.
//looks like have to continue to decompose addresses after all,
//e.g. rdspace is always used even if no reads;  and creqw always used
//even if no writes...sigh...
//
		if (test_mode0) begin
			rbcrptr <= 4'b0000;
		end
                else if ((steprbcrptr & !rdfillmode) || (stepreaddd &
		  rdenwritec & !rdenreadc & !rdenreadz)) begin
                        rbcrptr <= rbcrptr + rbcrinc;
		end
                else if (steprbzrptr & !rdfillmode) begin
//step color read ptr if z reads but no c reads, and c writes
                        rbcrptr <= (!rdenreadc & rdenwritec) ?
                                (rbcrptr + rbcrinc) : rbcrptr;
                end

                if (test_mode0) begin
                        rbzrptr <= 4'b0000;
                end
                else if ((steprbzrptr & !rdfillmode) || (stepreaddd &
                  rdenwritez & !rdenreadz & !rdenreadc)) begin
                        rbzrptr <= rbzrptr + rbzrinc;
		end
                else if (steprbcrptr & !rdfillmode) begin
//step z read ptr if c read, no z read, with z writes
                        rbzrptr <= (!rdenreadz & rdenwritez) ?
                                (rbzrptr + rbzrinc) : rbzrptr;
                end

                if (test_mode0) begin
                        rbcwptr <= 4'b1000;
                end
                else if ((steprbcwptr || (!(wrenwritec || wrenwritez || stopgclock) &
		  wrenreadc & (endspant14 || fullcwmt11))) & !wrfillmode) begin
                        rbcwptr <= rbcwptr + rbcwincwr;
//above now never hit, and t14 is bogus (see z)....
//step color read ptr if no c/z reads case
                end
                else if (steprbzwptr & !wrfillmode) begin
//the following case not used, as loads are not z buffered...leave for now tho;
                        rbcwptr <= (wrenreadc & !wrenwritec) ?
                                (rbcwptr + rbcwincwr) : rbcwptr;
                end

                if (test_mode0) begin
                        rbzwptr <= 4'b1000;
                end
                else if ((steprbzwptr || (!stopgclock &
                  wrloadmode & (endspant12 || (fullzwmt11)))) & !wrfillmode) begin
                         rbzwptr <= rbzwptr + rbzwincwr;
                end

		rbcrptrd <= rbcrptr;
		rbzrptrd <= rbzrptr;
		rbcwptrd <= rbcwptr;
		rbzwptrd <= rbzwptr;
		stallwrctxtd <= stallwrctxt;
		stallrdctxtd <= stallrdctxt;

//note:  all *xf values only need to be 12 lsb's************************
//below:  rddone is kept set until span is prep'd to byte address;  then
//then it is kept low until we encounter last spanlet (via lastone set);
//however, if primitive has no reads req'd, we set rddone as soon as the
//address context is passed onto rmwctxt, thus allowing next span processing;
	
		if (spanproc) begin
			rddone <= low;
		end
		else if (startspant1 & !stopgclock & rdfillmode) begin
			rddone <= high;
		end
		else if (steprddone || enstepread &
			stepread) begin

			rddone <= lastonee;
		end
		else if (!spanproc & !(startspant1 & !stopgclock & rdfillmode) &
			!steprddone & !(enstepread &
					(stepread))) begin
			rddone <= rddone;
		end
		else begin
			rddone <= 'bx;
		end

//that following is to step read ptrs if write only op.....

		if (enstepread) begin
			stepread <= state_idle & rdspace &
				!rddone & !stepreadd & !stepreaddd & !stepread;
		end
		else if (!enstepread) begin
			stepread <= low;
		end
		else begin
			stepread <= 'bx;
		end

		stepreadd <= stepread;
		stepreaddd <= stepreadd;

		if (stepread) begin

			enstepread <= !lastonee;

		  if (!lastone) begin
			maskrddone <= low;
//                        rdcxi <= {({rdcxi[25:7], fc1} +
//                          {{19{rdxdec}}, fc2} + {20'b0, ~rdxdec}), {5{rdxdec}}};
//                        rdzxi <= {({rdzxi[25:7], fz1} +
//                          {{19{rdxdec}}, fz2} + {21'b0, ~rdxdec}), {4{rdxdec}}};
            rdcxi_addend0 = {rdcxi[25:7],  fc1, 4'b1111,    1'b1};
            rdcxi_addend1 = {{19{rdxdec}}, fc2, 4'b0000, ~rdxdec};
            rdzxi_addend0 = {rdzxi[25:7],  fz1, 3'b111,    1'b1};
            rdzxi_addend1 = {{19{rdxdec}}, fz2, 3'b000, ~rdxdec};
		  end
		end
                else if (stepreadd) begin
                          if (!lastonee) begin
                                rbcountcr <= (({7{rdxdec}} ^~ rdcxi[6:0]) &
					{1'b0, (cnum8), 5'h1f});
                                rbcountzr <= (({7{rdxdec}} ^~ rdzxi[6:0]) &
					{1'b0, znum8, (znum8 || znum4), 4'hf});
                          end
                          else if (lastonee) begin
                                rbcountcr <= (({7{rdxdec}} ^~ (rdcxi[6:0] +
                                        ~rdcxf[6:0])) + {6'b0, rdxdec});
                                rbcountzr <= (({7{rdxdec}} ^~ (rdzxi[6:0] +
                                        ~rdzxf[6:0])) + {6'b0, rdxdec});
                          end
		end
		else if (stepreaddd) begin
                  rbcrinc <= ((rbcountcr + ({4{rdxdec}} ^ rdcxi[3:0])) >> 4) + 1;
                  rbzrinc <= ((rbcountzr + ({4{rdxdec}} ^ rdzxi[3:0])) >> 4) + 1;

                  fc1 <= {(rdcxi[6]),
                                (cnum4 ? rdcxi[5] : rdxdec)};
                  fz1 <= {(rdzxi[6]),
                                ((znum4 || znum2) ? rdzxi[5] : rdxdec),
				(znum2 ? rdzxi[4] : rdxdec)};
                  fc2 <= {(rdxdec), (rdxdec ^~ cnum4)};
                  fz2 <= {(rdxdec), (rdxdec ^~ (znum4 || znum2)),
				(rdxdec ^~ znum2)};
		  lastone <= lastonee;
		end


//rd2rmw indicates rdctxt has been copied to rmwctxt;  we must wait for this
//	event before we can start fetching the next span.

                if (spanproc) begin
                        rdy4span <= high;
		end
                else begin
                        rdy4span <= low;
		end

		if (startspant1) begin
			stallrden <= high;
		end
		else if (rdy4span) begin
			stallrden <= low;
		end
		else if (!startspant1 & !rdy4span) begin
			stallrden <= stallrden;
		end
		else begin
			stallrden <= 'bx;
		end

//READCTXT STATE MACHINE
      case (state)
         state_idle : begin
            	if (!spanbufmt & rddone & rd2rmw) begin
			rd2rmw <= low;
			spanbufrd <= high;
               		rdcxi_addend0 = { 6'b0, nextspanxi };
               		rdcxf_addend0 = { 6'b0, nextspanxf };
                	rdxdec <= nextspanxdec;
			pixcount <= nextspancount;
                	spanproc <= high;
			state <= state_byte;
// synopsys translate_off
`ifdef MSPAN_MON
idle_arcs <= { 1'b1 | idle_arcs };		    // A
`endif
// synopsys translate_on
//now calc/store attributes so use directly from reg:
			rdcsize8 <=
		 	 (load_en ? (tex_size == 'h1) : (color_size == 'h1));
			rdcsize16 <=
			 (load_en ? (tex_size == 'h2) : (color_size == 'h2));
			rdcsize32 <=
			 (load_en ? (tex_size == 'h3) : (color_size == 'h3));
			rdfillmode <= !load_en & (cycle_type == 'h3);
			rdloadmode <= load_en;
			rdloadtlut <= ldtlut_en;
                        rdenreadc <= image_read_en & !load_en;
                        rdenreadz <= z_compare_en || load_en;
			rdenwritec <= !load_en & !(cycle_type == 'h2);
			rdenwritez <= (z_update_en || (cycle_type == 'h2)) &
								!load_en;
			rdcopymode <= (cycle_type == 'h2) & !load_en;
			rdtwophase <= (cycle_type == 'h1) & !load_en;
			rdrgbmode <= (load_en ? (tex_format == 'h0) :
					(color_format == 'h0));
 	             	end
		else if (spanbufmt || !rddone || !rd2rmw) begin
			state <= state_idle;
// synopsys translate_off
`ifdef MSPAN_MON
idle_arcs <= { { 1'b1, 1'b0 } | idle_arcs };	    // B
`endif
// synopsys translate_on
			end
	    	end

	state_byte : begin
         case (1'b1) // synopsys parallel_case full_case
         rdcsize8 : begin
            rdcxi_addend0 = rdcxi;
            rdcxf_addend0 = rdcxf;
         end
         rdcsize16 : begin
            rdcxi_addend0 = {rdcxi, rdxdec};
            rdcxf_addend0 = {rdcxf, ~rdxdec};
         end
         rdcsize32 : begin
            rdcxi_addend0 = {rdcxi, rdxdec, rdxdec};
            rdcxf_addend0 = {rdcxf, ~rdxdec, ~rdxdec};
         end
         default : begin
            $display("Something horrible has gone wrong in %m");
            $finish;
            end
         endcase
         rdcxi_addend1 = rdloadmode ? tex_base : color_base;
         rdcxf_addend1 = rdloadmode ? tex_base : color_base;

         rdzxi_addend0 = {rdcxi,  rdxdec};
         rdzxf_addend0 = {rdcxf, ~rdxdec};
         rdzxi_addend1 = z_base;
         rdzxf_addend1 = z_base;

			state <= state_spanlet;
			spanbufrd <= low;
			stepcount <= {12{rdxdec}} ^~ (rdcxi + (~rdcxf) + rdxdec);
                        cnum4 <= (rdenwritez || rdenreadz) & (rdcsize8) ||
				rdcsize32 & rdenreadc & !rdtwophase;
			cnum8 <= !(((rdenwritez || rdenreadz) & rdcsize8) ||
                                rdcsize32 & rdenreadc & !rdtwophase);
			znum2 <= rdcsize32 & rdenreadc & !rdtwophase &
						!rdloadmode;
                      znum4 <= rdcsize32 & (!rdenreadc || rdtwophase) &
                                               !rdloadmode;
                      znum8 <= !(rdcsize32 & (rdenreadc || rdenwritec))
                                              || rdloadmode;
		rdperclk8 <= (rdfillmode || rdloadmode) & rdcsize8;
		rdperclk4 <= rdcopymode || ((rdfillmode ||
					rdloadmode & !rdloadtlut) & rdcsize16);
		rdperclk2 <= (rdfillmode || rdloadmode) & rdcsize32;

//note:  if loadmode & loadtlut, rdpix ptrs must be 1/clk as well as nextcount 
//  below, we use perclk but as it's not yet latched we regress: 2,4,8,else.

		if ((rdfillmode || rdloadmode) & rdcsize32) begin
			pixcount <= pixcount + rdcxi[0];
		end
		else if ((rdfillmode ||
                          	(!rdloadtlut & rdloadmode)) & rdcsize16 ||
				rdcopymode) begin
			pixcount <= pixcount + rdcxi[1:0];
		end
		else if ((rdfillmode || rdloadmode) & rdcsize8) begin
			pixcount <= pixcount + rdcxi[2:0];
		end
		else begin 
			pixcount <= pixcount;
		end
	end

	state_spanlet : begin
		if (spanproc) begin
			savecxi <= rdcxi;
			maskrddone <= stepcount[9];
			rdmaskdone <= stepcount[9];
                        state <= state_spanlet2;
// synopsys translate_off
`ifdef MSPAN_MON
spanlet_arcs <= { 1'b1 | spanlet_arcs };	    // A
`endif
// synopsys translate_on
                     rdrbcrptr <= rbcrptr[3:0];
                     rdrbzrptr <= rbzrptr[3:0];
                        enstepread <= !rdfillmode & (rdenwritec || rdenwritez) &                                                !(rdenreadc || rdenreadz);
		  if (rdloadmode || rdcopymode) begin
                        savezxi <= rdcxi;
               		rdzxi_addend0 = rdcxi;
               		rdzxf_addend0 = rdcxf;
		  end
		  else begin
			savezxi <= rdzxi;
		  end
		end
		
		else if (enstepread) begin
			state <= state_idle;
// synopsys translate_off
`ifdef MSPAN_MON
spanlet_arcs <= { { 1'b1, 1'b0 } | spanlet_arcs };  // B
`endif
// synopsys translate_on
                        rbcrinc <= ((rbcountcr + ({4{rdxdec}} ^ rdcxi[3:0])) >> 4) + 1;
                        rbzrinc <= ((rbcountzr + ({4{rdxdec}} ^ rdzxi[3:0])) >> 4) + 1;
		end
                else if (!spanproc & (steprbcrptr & rdenwritez & !rdenreadz ||
			steprbzrptr & rdenwritec & !rdenreadc) &
				!rddone & !lastoneed) begin
//                        rdcxi <= {({rdcxi[25:7], fc1} +
//                          {{19{rdxdec}}, fc2} + {20'b0, ~rdxdec}), {5{rdxdec}}};
//                        rdzxi <=  {({rdzxi[25:7], fz1} +
//                          {{19{rdxdec}}, fz2} + {21'b0, ~rdxdec}), {4{rdxdec}}};
            rdcxi_addend0 = {rdcxi[25:7],  fc1, 4'b1111,    1'b1};
            rdcxi_addend1 = {{19{rdxdec}}, fc2, 4'b0000, ~rdxdec};
            rdzxi_addend0 = {rdzxi[25:7],  fz1, 3'b111,    1'b1};
            rdzxi_addend1 = {{19{rdxdec}}, fz2, 3'b000, ~rdxdec};
			maskrddone <= low;
                        state <= state_spanlet2;
// synopsys translate_off
`ifdef MSPAN_MON
spanlet_arcs <= { 1'b1, 2'b0 } | spanlet_arcs;	    // C
`endif
// synopsys translate_on
                        end
		else if (!spanproc & steprbcrptr & !rddone & !lastoneed) begin
//			rdcxi <= {({rdcxi[25:7], fc1} + 
//			  {{19{rdxdec}}, fc2} + {20'b0, ~rdxdec}), {5{rdxdec}}};
            rdcxi_addend0 = {rdcxi[25:7],  fc1, 4'b1111,    1'b1};
            rdcxi_addend1 = {{19{rdxdec}}, fc2, 4'b0000, ~rdxdec};
			maskrddone <= low;
		  if (!rdenreadz) begin
                        state <= state_spanlet2;
// synopsys translate_off
`ifdef MSPAN_MON
spanlet_arcs <= { 1'b1, 3'b0 } | spanlet_arcs;	    // D
`endif
// synopsys translate_on
		  end
                  else if (rdenreadz) begin
                        state <= state_spanlet;
// synopsys translate_off
`ifdef MSPAN_MON
spanlet_arcs <= { 1'b1, 4'b0 } | spanlet_arcs;	    // E
`endif
// synopsys translate_on
                  end
			end
                else if (!spanproc & steprbzrptr & !rddone & !lastoneed) begin
//                        rdzxi <= {({rdzxi[25:7], fz1} +
//                          {{19{rdxdec}}, fz2} + {21'b0, ~rdxdec}), {4{rdxdec}}};
            rdzxi_addend0 = {rdzxi[25:7],  fz1, 3'b111,    1'b1};
            rdzxi_addend1 = {{19{rdxdec}}, fz2, 3'b000, ~rdxdec};
			maskrddone <= low;
                        state <= state_spanlet2;
// synopsys translate_off
`ifdef MSPAN_MON
spanlet_arcs <= { 1'b1, 5'b0 } | spanlet_arcs;	    // F
`endif
// synopsys translate_on
			end
                else if (!spanproc & steprbcrptr & !rddone & lastoneed) begin
		  if (!rdenreadz) begin
                        state <= state_spanlet2;
// synopsys translate_off
`ifdef MSPAN_MON
spanlet_arcs <= { 1'b1, 6'b0 } | spanlet_arcs;	    // G
`endif
// synopsys translate_on
                  end
                  else if (rdenreadz) begin
                        state <= state_spanlet;
// synopsys translate_off
`ifdef MSPAN_MON
spanlet_arcs <= { 1'b1, 7'b0 } | spanlet_arcs;	    // H
`endif
// synopsys translate_on
                  end
                        end
                else if (!spanproc & steprbzrptr & !rddone & lastoneed) begin
                        state <= state_spanlet2;
// synopsys translate_off
`ifdef MSPAN_MON
spanlet_arcs <= { 1'b1, 8'b0 } | spanlet_arcs;	    // I
`endif
// synopsys translate_on
                        end
		else if (!spanproc & rddone) begin
			state <= state_idle;
// synopsys translate_off
`ifdef MSPAN_MON
spanlet_arcs <= { 1'b1, 9'b0 } | spanlet_arcs;	    // J
`endif
// synopsys translate_on
			end
		else if (!spanproc & !steprbcrptr & !steprbzrptr &!rddone) begin
			state <= state_spanlet;
// synopsys translate_off
`ifdef MSPAN_MON
spanlet_arcs <= { 1'b1, 10'b0 } | spanlet_arcs;	    // K
`endif
// synopsys translate_on
//	here we calc the # 72b (64b) aligned regfile entries the request uses
			rbcrinc <= ((rbcountcr + ({4{rdxdec}} ^ rdcxi[3:0])) >> 4) + 1;
			rbzrinc <= ((rbcountzr + ({4{rdxdec}} ^ rdzxi[3:0])) >> 4) + 1;
			end
		end
//z only 4 or 8 words per access (c 4 or 8 or 16 words)

			
//assumed:  c/zorigin 64b word aligned;  pixels pixel-wise aligned;
//		max count/mem space per span is 4K bytes, aligned
		
	state_spanlet2 : begin
			spanproc <= low;
                        fc1 <= {(rdcxi[6]),
                                (cnum4 ? rdcxi[5] : rdxdec)};
                        fz1 <= {(rdzxi[6]),
                                ((znum4 || znum2) ? rdzxi[5] : rdxdec),
				(znum2 ? rdzxi[4] : rdxdec)};
                        fc2 <= {(rdxdec), (rdxdec ^~ cnum4)};
                        fz2 <= {(rdxdec), (rdxdec ^~ (znum4 || znum2)),
				(rdxdec ^~ znum2)};
			state <= state_spanlet;
		if (!lastonee) begin
                        rbcountcr <= (({7{rdxdec}} ^~ rdcxi[6:0]) & {1'b0,
                                (cnum8), 5'h1f});
                        rbcountzr <= (({7{rdxdec}} ^~ rdzxi[6:0]) & {1'b0,
				znum8, (znum8 || znum4), 4'hf});
			end
		else if (lastonee) begin
                        rbcountcr <= (({7{rdxdec}} ^~ (rdcxi[6:0] +
                                ~rdcxf[6:0])) + {6'b0, rdxdec});
                        rbcountzr <= (({7{rdxdec}} ^~ (rdzxi[6:0] +
                                ~rdzxf[6:0])) + {6'b0, rdxdec});
			end

	  lastone <= lastonee;

	end

	default :
			state <= 4'bx;
         endcase

//WRITE CONTEXT STATE
//writes always 8 words c/z
//the following must be non-stallable clock regime:

        if ((wrbusy & (!(creqw || zreqw) || (resetcreqw & !zreqw || resetzreqw))
		& wrdone) || (lastonew & steprbcwptr & (!wrenwritez &
			!wrenreadz) ||
		steprbzwptr & lastonewz)) begin

         wrcxi <= wrcxi_buf;
	 wrmaskdonec <= wrmaskdone_buf;
	end
	else if (((!resetcreqw & steprbcwptr ) ||
		  (!(wrenwritec || wrenwritez || stopgclock) &
		  fullcwmt11) & !wrfillmode & !lastonew) ||
		  (resetcreqw & steprbcwptr & !lastonew)) begin

		wrcxi <= wrcxi_addend0 + wrcxi_addend1; // synopsys label wrcxi

/*
		if (!wrrender) begin
                                wrcxi_addend0 = { wrcxi[25:6],    1'b1,    5'b00000};
                                wrcxi_addend1 = {{20{wrxdec}}, ~wrxdec, {5{wrxdec}}};
		end
		else begin
                                wrcxi_addend0 = { wrcxi[25:5],    1'b1,     4'b0000};
                                wrcxi_addend1 = {{21{wrxdec}}, ~wrxdec, {4{wrxdec}}};
         end
*/
		wrmaskdonec <= low;
	end

        if ((wrbusy & (!(creqw || zreqw) || (resetcreqw & !zreqw || resetzreqw))
		& wrdone) || (lastonew & steprbcwptr & (!wrenwritez &
			!wrenreadz) ||
		steprbzwptr & lastonewz)) begin

		wrzxi <= wrzxi_buf;
		wrmaskdonez <= #1 wrmaskdone_buf;
	end
	else if (((!resetzreqw & steprbzwptr) ||
		(!(!wrloadmode || stopgclock) &
		fullzwmt11) & !wrfillmode & !lastonewz) ||
		((resetzreqw & steprbzwptr & !lastonewz))) begin

                wrzxi <= wrzxi_addend0 + wrzxi_addend1; // synopsys label wrzxi

/*
		if (!wrrender) begin
                                wrzxi_addend0 = { wrzxi[25:6],    1'b1,    5'b00000};
                                wrzxi_addend1 = {{20{wrxdec}}, ~wrxdec, {5{wrxdec}}};
         end
		else begin
                                wrzxi_addend0 = { wrzxi[25:5],    1'b1,     4'b0000};
                                wrzxi_addend1 = {{21{wrxdec}}, ~wrxdec, {4{wrxdec}}};
         end
*/
		wrmaskdonez <= low;
	end

        if ((wrbusy & (!(creqw || zreqw) || (resetcreqw & !zreqw || resetzreqw))
		  & wrdone) || (lastonew & steprbcwptr & !(wrenwritez || wrenreadz) ||
		  steprbzwptr & lastonewz)) begin
                        wrcxf <= #1 wrcxf_buf;
                        wrzxf <= #1 wrzxf_buf;
                        wrxdec <= #1 wrxdec_buf;
			wrenreadc <= #1 wrenreadc_buf;
			wrenreadz <= #1 wrenreadz_buf;
			wrenwritec <= #1 wrenwritec_buf;
			wrenwritez <= #1 wrenwritez_buf;
			wrfillmode <= #1 wrfillmode_buf;
			wrloadmode <= #1 wrloadmode_buf;
			wrcopymode <= #1 wrcopymode_buf;
			wrfillcolor <= #1 fillcolor;
			wrrender <= #1 wrrender_buf;
                        end

        if ((wrbusy & (!(creqw || zreqw) || (resetcreqw & !zreqw || resetzreqw))
              & wrdone) || (wrbusy) & ((lastonew & steprbcwptr & !(wrenwritez ||
			wrenreadz)) ||
					(lastonewz & steprbzwptr))) begin
                        wrdone <= #1 low;
                        end
                else if (((lastonew & steprbcwptr & !(wrenwritez || wrenreadz)) ||
				(lastonewz & steprbzwptr)) || (wrloadmode &
					endspant12 & !stopgclock)) begin
                        wrdone <= #1 high;
                        end

//the above relies on the fact that, if writes are done, they are sync'd
//for all applicable planes via wmask pipe equalization, so that by looking
//at the OR of the steprb*wptr's we indeed catch the last write event OK.
//else if no writes are called for, we immediately assert wrdone and thus don't
//block future spans at this context boundary (wr_buf => wr).
// fix 9/26/94:  and with !enwritez so that we wait for last write to occur 1st;

//the above can be handled simply by being gclock (stallable clock) regime?****
//then don't need wrbusy in the equation...

//below wrbusy cannot be gclock, as it is a stall component of stallwrctxt;

       if ((wrbusy  & (!(creqw || zreqw) || (resetcreqw & !zreqw || resetzreqw))
	  & wrdone) || (wrbusy & ((lastonew & steprbcwptr & !(wrenwritez ||
			wrenreadz)) ||
				(lastonewz & steprbzwptr)))) begin
                        wrbusy <= #1 low;
	end

	else if (startspant7m & !wrbusy & !stopgclock) begin
                        wrbusy <= #1 high;
	end

                rbcwincwr <= ((rbcountcw + ({4{wrxdec}} ^ wrcxi[3:0])) >> 4) + 1;
                rbzwincwr <= ((rbcountzw + ({4{wrxdec}} ^ wrzxi[3:0])) >> 4) + 1;

		smcwincwr <= ((rbcountcw + ({3{wrxdec}} ^ wrcxi[2:0])) >> 3) + 1;
                smzwincwr <= ((rbcountzw + ({3{wrxdec}} ^ wrzxi[2:0])) >> 3) + 1;

	lastonew <= lastonewe;
	lastonewz <= lastonewez;

//use lastonew early because need length set for next rdram req immediately

		if (!lastonewe) begin
			rbcountcw <= ({6{wrxdec}} ^~ wrcxi[5:0]) &
						{~wrrender, 5'b11111};
			end
		else if (lastonewe) begin
                        rbcountcw <= ({6{wrxdec}} ^~ (wrcxi[5:0] +
                                ~wrcxf[5:0] + {5'b0, wrxdec}));
			end

                if (!lastonewez) begin
                        rbcountzw <= ({6{wrxdec}} ^~ wrzxi[5:0]) &
						{~wrrender, 5'b11111};
                        end
                else if (lastonewez) begin
                        rbcountzw <= ({6{wrxdec}} ^~ (wrzxi[5:0] +
                                ~wrzxf[5:0] + {5'b0, wrxdec}));
                        end

      rdcxi <= rdcxi_addend0 + rdcxi_addend1; // synopsys label rdcxi
      rdcxf <= rdcxf_addend0 + rdcxf_addend1; // synopsys label rdcxf
      rdzxi <= rdzxi_addend0 + rdzxi_addend1; // synopsys label rdzxi
      rdzxf <= rdzxf_addend0 + rdzxf_addend1; // synopsys label rdzxf

//     wrcxi <= wrcxi_addend0 + wrcxi_addend1; // synopsys label wrcxi
//     wrzxi <= wrzxi_addend0 + wrzxi_addend1; // synopsys label wrzxi
	end
end

endmodule