ms_si.ss
4.32 KB
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/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = ms_si
wire_load = 256000
standard_load = 0.01
clock = clock
clocks = { clock gclock }
default_input_delay = 2.0
default_output_delay = 13.0
default_input_load = 20
default_output_load = 20
default_drive_cell = dfntnh
default_drive_pin = q
default_period = 16.0
default_max_transition = 1.5
default_uncertainty = 1.0
/*****************************************************************************/
/* set the path and read */
/*****************************************************************************/
search_path = search_path + "../src" + "../../syn" + "../../inc"
read -f verilog ms_latch_h.v
read -f verilog ms_latch_l.v
read -f verilog ms_latch8n.v
read -f verilog ms_latch10n.v
read -f verilog ms_latch72.v
read -f verilog ms_latch144.v
read -f verilog module + .v
current_design = module
/*****************************************************************************/
/* default environment */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/*****************************************************************************/
/* clock constraints */
/*****************************************************************************/
create_clock clocks -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -uncertainty default_uncertainty clocks
set_dont_touch_network clocks
/*****************************************************************************/
/* default constraints */
/*****************************************************************************/
set_max_area 0
set_dont_touch { ne35hd130d/nt01d* }
set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null
set_drive 0 { clocks reset_l }
set_input_delay 0 clocks
set_false_path -from reset_l
set_max_transition default_max_transition current_design
/*****************************************************************************/
/* custom constraints */
/*****************************************************************************/
set_driving_cell -cell ni01d5 { dma_read_en }
set_input_delay 5.0 -clock clock { dma_read_en }
set_input_delay 12.0 -clock clock { dbus_din ebus_din }
set_output_delay 6.0 -clock clock { dbus_dout ebus_dout }
set_input_delay 4.5 -clock clock { limitcw limitzw }
set_input_delay 5.0 -clock clock { dout }
set_output_delay 3.0 -clock clock { din }
set_output_delay 10.0 -clock clock { addr0 addr1 }
set_output_delay 10.0 -clock clock { we0 we1 }
set_output_delay 10.0 -clock clock { stallrw }
set_output_delay 10.0 -clock clock { stallphase }
set_output_delay 10.0 -clock clock { rdprcolor }
set_min_porosity 75
/*****************************************************************************/
/* check */
/*****************************************************************************/
link
check_design > module + ".lint"
/*****************************************************************************/
/* compile */
/*****************************************************************************/
compile -ungroup_all -routability
/*****************************************************************************/
/* write */
/*****************************************************************************/
include "report.dc"
write -format edif -hierarchy -o module + ".edf" module
write -format db -hierarchy -o module + ".db" module
quit