div.ss 2.7 KB
/*****************************************************************************/
/* custom variables                                                          */
/*****************************************************************************/
wire_load = 256000
clocks = { "gclk" }
standard_load = 0.01
default_input_delay = 1.5
default_output_delay = 4.0
default_input_load = 20
default_output_load = 20
default_drive_cell = "dfntnh"
default_drive_pin = "q"
default_period = 16.0
default_max_transition = 1.5
default_uncertainty = 1.0

/*****************************************************************************/
/* set the path and read                                                     */
/*****************************************************************************/
search_path = search_path + "../../../syn" + ".."

read -f db ../rcp_partition.db

/*****************************************************************************/
/* div top-level netlist                                                     */
/*****************************************************************************/
module = "div"
current_design = module

link
check_design > module + ".lint"

include "cadence_defaults.dc"

/* write out the top-level block hierarchy in one edif file */
write -format edif -o module + ".edf" module

/*****************************************************************************/
/* div_ctl level netlist                                                     */
/*****************************************************************************/
module = "divctl"
current_design = module

link
check_design > module + ".lint"

/*****************************************************************************/
/* constraints                                                               */
/*****************************************************************************/

/*****************************************************************************/
/* reports                                                                   */
/*****************************************************************************/

include "report.dc"

/*****************************************************************************/
/* netlist defaults for cadence                                              */
/*****************************************************************************/

include "cadence_defaults.dc"

/*****************************************************************************/
/* write design                                                              */
/*****************************************************************************/

/* write out the block hierarchy in one edif file */
write -format edif -hierarchy -o module + ".edf" module

quit