module = ls
current_design module

set_operating_conditions NOM -library rcp.db;

create_clock clk -period 16.0 -waveform {0 8.0};
set_input_delay 4.0 -clock clk all_inputs();
set_output_delay 2.0 -clock clk all_outputs();
set_clock_skew -uncertainty 1 clk;
set_drive 0 {clk};
set_load 1 all_outputs();

set_max_transition 2.00 current_design;

set_input_delay 8.0 -clock clk {reset_l};
set_input_delay 2.5 -clock clk {halt};
set_input_delay 4.0 -clock clk {iddq_test};

set_input_delay 14.0 -clock clk {rd_base};
set_input_delay 12.0 -clock clk {ls_drive_rd_base};
set_input_delay 12.0 -clock clk {rd_offset};
set_input_delay 8.0 -clock clk {rd_elem_num};
set_input_delay 9.5 -clock clk {address}; 
set_input_delay 2.0 -clock clk {df_ls_drive_ls_in_wb};
set_input_delay 2.0 -clock clk {df_pass_thru};
set_input_delay 2.0 -clock clk {su_ex_store};
set_input_delay 2.0 -clock clk {su_ex_load};
set_input_delay 2.0 -clock clk {vu_ex_store};
set_input_delay 2.0 -clock clk {vu_ex_load};
set_input_delay 2.0 -clock clk {ex_mtc2};
set_input_delay 2.0 -clock clk {ex_mfc2};
set_input_delay 2.0 -clock clk {ex_cfc2};
set_input_delay 3.0 -clock clk {cp0_write};
set_input_delay 15.0 -clock clk {vu_rd_ld_dec_k};
set_input_delay 15.0 -clock clk {vu_rd_st_dec_k};
set_input_delay 9.0 -clock clk {chip_sel};
set_input_delay 2.0 -clock clk {ex_su_byte_ls};
set_input_delay 2.0 -clock clk {ex_su_half_ls};
set_input_delay 2.0 -clock clk {ex_su_uns_ls};
set_input_delay 2.5 -clock clk {ex_dma_rd_to_dm};
set_input_delay 2.5 -clock clk {ex_dma_dm_to_rd};
set_input_delay 4.5 -clock clk {dma_wen}; 
set_input_delay 2.5 -clock clk {dma_address};
set_input_delay 1.5 -clock clk {dmem_dataout};
set_input_delay 13.0 -clock clk {mem_write_data};
set_input_delay 2.0 -clock clk {ex_mfc0};
set_input_delay 3.0 -clock clk {pc};
 
set_input_delay 4.0 -clock clk {ls_data};
set_input_delay 9.0 -clock clk {cp0_data};

set_driving_cell -cell ni01d5 -pin z {dmem_dataout};

set_output_delay -max 3.0 -clock clk {vu_bwe};
set_output_delay -max 0.5 -clock clk {df_chip_sel_l}; 
set_output_delay -max 11.0 -clock clk {df_wen_l}; 
set_output_delay -max 11.0 -clock clk {df_addr_low};
set_output_delay -max 9.5 -clock clk {df_addr_high};
set_output_delay -max 7.5 -clock clk {dmem_rd_data};
set_output_delay -max 6.0 -clock clk {df_datain}; 
set_output_delay -max 0.1 -clock clk {debug_df_dma_rd_to_dm}; 

set_output_delay -max 4.0 -clock clk {ls_data};
set_output_delay -max 7.0 -clock clk {cp0_data};

set_load 1.6 {vu_bwe};
set_load 2.0 {ls_data};
set_load .7 {cp0_data};
set_load 1.5 {dmem_rd_data};

set_max_fanout 0.02 { reset_l }

group_path -name non_dmem_rd_group -to all_outputs();
group_path -default -to {dmem_rd_data, ls_data};
group_path -name dmem_rd_group -to {dmem_rd_data};
group_path -name ls_data_group -to {ls_data};

set_false_path -from "dmem_dataout*" -to "*vu_ed_datain_ff*"
set_false_path -from "lsctl_vu_dw_rot_ff*" -to "*vu_ed_datain_ff*"
set_false_path -from "lsctl_vu_dw_ld_dec_ff*" -to "*vu_ed_datain_ff*"
set_false_path -from "lsctl_pass_thru_ff*" -to  "*vu_ed_datain_ff*"
set_false_path -from "lsctl_ls_dw_suld_ff*" -to "*vu_ed_datain_ff*"
set_false_path -from "lsdp_vu_dw_half_ff*" -to "*vu_ed_datain_ff*"
set_false_path -from "lsdp_vu_dw_byte_ff*" -to "*vu_ed_datain_ff*"
set_false_path -from "lsctl_ls_dw_mfc2_ff*" -to "*vu_ed_datain_ff*"
set_false_path -from "lsctl_ls_dw_cfc2_ff*" -to "*vu_ed_datain_ff*"
set_false_path -from "lsctl_vu_dw_uns_ff*" -to "*vu_ed_datain_ff*"

set_false_path -from "dmem_dataout*" -to "cp0_data*"
set_false_path -from "lsctl_vu_dw_rot_ff*" -to "cp0_data*"
set_false_path -from "lsctl_vu_dw_ld_dec_ff*" -to "cp0_data*"
set_false_path -from "lsctl_pass_thru_ff*" -to  "cp0_data*"
set_false_path -from "lsctl_ls_dw_suld_ff*" -to "cp0_data*"
set_false_path -from "lsdp_vu_dw_half_ff*" -to "cp0_data*"
set_false_path -from "lsdp_vu_dw_byte_ff*" -to "cp0_data*"
set_false_path -from "lsctl_ls_dw_mfc2_ff*" -to "cp0_data*"
set_false_path -from "lsctl_ls_dw_cfc2_ff*" -to "cp0_data*"
set_false_path -from "lsctl_vu_dw_uns_ff*" -to "cp0_data*"