notes on ms_grp setup/hold time analysis

for now, the issue is HOLD time:

	proposed methodology:

		because synopsys can't handle skew greater
		than min clk to Q delay (if so, gives error
		report for clk and Q of SAME element!!!)
		must resort to alternate approach.  also,
		doesn't handle domain crossings or additive
		skew between domains.


	1.  clk and gclk skews:  run analysis with single clk skews
		only (not domain crossing values) to get within domain
		analysis.

	2.  now do domain crossing analysis:

		a.  run with cross skew on clk only; save results.
		b.  ditto for gclk only.
		c.  ditto for both clocks.
		d.  log entries for single clock can be removed from both
			clock log.  
		e.  the remaining log entries are domain crossings.

hmmm....no script or filter for this yet.  will do manually to fully
verify the approach works first....

	in the final verification phase, actual clock net delays will
	be modelled (with some granularity) and will supersede the above
	results.  also, above results will not cause logic changes for
	synth.