pi_controller.ss 5.29 KB
/************************************************************************/
/* SYNOPSIS SCRIPT                                                      */
/************************************************************************/

/************************************************************************/
/* Synthesis parameters                                                 */
/************************************************************************/
module                  = pi_controller
clock                   = clock
wire_load               = 256000
standard_load           = 0.01
dflt_input_delay        = 2.0
dflt_output_delay       = 14.0
dflt_input_load         = 20
dflt_output_load        = 20
dflt_drive_cell         = dfntnh
dflt_drive_pin          = q
dflt_max_transition	= 1.5

/************************************************************************/
/* Establish search path and read in source files                       */
/************************************************************************/
search_path = {. \
	/ecad/synopsys/current/libraries/syn \
	/ecad/reality/lib/synopsys/nec35_v2.1 \
	/ecad/reality/lib/synopsys/rcp_lib};

search_path = search_path                       \
                + "../src"                      \
                + "../../inc"                   \
                + "../../../lib/verilog/user"   \
                + "../../syn"

read -f verilog dbus_driver.v
read -f verilog module + ".v"
current_design = module

/************************************************************************/
/* Clock and reset constraints                                          */
/************************************************************************/
create_clock            clock -period 16.0 -waveform {0.0 8.0}
set_dont_touch_network  clock

/************************************************************************/
/* Default synthesis constraints                                        */
/************************************************************************/
/* set_max_area            6000 */
set_dont_touch          { ne35hd130d/nt01d* }
set_input_delay         dflt_input_delay -clock clock all_inputs()
set_load                dflt_input_load * standard_load all_inputs()
set_output_delay        dflt_output_delay -clock clock all_outputs()
set_load                dflt_output_load * standard_load all_outputs()
set_driving_cell        -cell dflt_drive_cell -pin dflt_drive_pin all_inputs()
set_max_transition	dflt_max_transition current_design
set_drive               0 clock
set_driving_cell        -none clock
set_arrival             0 clock
set_drive               0 reset_l
set_driving_cell        -none reset_l
set_input_delay         8 -clock clock reset_l

/************************************************************************/
/* Default operating conditions and environment                         */
/************************************************************************/
set_operating_conditions NOM
set_wire_load           wire_load -mode top

/************************************************************************/
/* Module specific timing constraints                                   */
/************************************************************************/
set_load                400 * standard_load     { tbw_dbu_data }
set_input_delay		5.0 -clock clock	{ icw_dbu_oenb }
set_input_delay         10.0 -clock clock        { tbw_dbu_data }
set_output_delay        6.0 -clock clock        { tbw_dbu_data }
set_input_delay         5.0 -clock clock        { idw_buf_dout }
set_output_delay        6.0 -clock clock        { odw_reg_rdata }
set_driving_cell        -cell nt01d5            { tbw_dbu_data }
set_driving_cell        -cell ni01d7            { icw_dma_start icw_dma_last }
set_load                400 * standard_load     { icw_dma_start icw_dma_last }
set_max_fanout          10 * standard_load      { icw_dma_start icw_dma_last }
set_load 0.4 { osr_pic_intr }
set_load 0.5 { ocr_dma_req }
set_load 3.2 { osr_adb_aleh }
set_load 3.2 { osr_adb_alel }
set_load 2.0 { ocr_adb_oenb_l }
set_load 2.0 { osr_adb_rd_l }
set_load 2.0 { osr_adb_wr_l }
set_load 0.5 { ocr_dma_req }
set_dont_touch uocr_buf_wenb

/************************************************************************/
/* Check design before compile                                          */
/************************************************************************/
check_design > module + ".lint"

/************************************************************************/
/* Compile                                                              */
/************************************************************************/
compile -map_effort high -ungroup_all

/************************************************************************/
/* Report results                                                       */
/************************************************************************/
include "report.dc"
report_constraint -all_violators

/************************************************************************/
/* Generate synthesis outputs                                           */
/************************************************************************/
write -format edif    -hierarchy -o module + ".edf"  module
write -format verilog -hierarchy -o module + ".vsyn" module
write -format db      -hierarchy -o module + ".db"   module

quit