pi_dma.ss
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/************************************************************************/
/* SYNOPSIS SCRIPT */
/************************************************************************/
/************************************************************************/
/* Synthesis parameters */
/************************************************************************/
module = pi_dma
clock = clock
wire_load = 256000
standard_load = 0.01
dflt_input_delay = 2.0
dflt_output_delay = 14.0
dflt_input_load = 20
dflt_output_load = 20
dflt_drive_cell = dfntnh
dflt_drive_pin = q
dflt_max_transition = 1.5
/************************************************************************/
/* Establish search path and read in source files */
/************************************************************************/
search_path = {. \
/ecad/synopsys/current/libraries/syn \
/ecad/reality/lib/synopsys/nec35_v2.1 \
/ecad/reality/lib/synopsys/rcp_lib};
search_path = search_path \
+ "../src" \
+ "../../inc" \
+ "../../../lib/verilog/user" \
+ "../../syn"
read -f verilog cbus_driver.v
read -f verilog module + ".v"
current_design = module
/************************************************************************/
/* Clock and reset constraints */
/************************************************************************/
create_clock clock -period 16.0 -waveform {0.0 8.0}
set_dont_touch_network clock
/************************************************************************/
/* Default synthesis constraints */
/************************************************************************/
set_max_area 700
set_dont_touch { ne35hd130d/nt01d* }
set_input_delay dflt_input_delay -clock clock all_inputs()
set_load dflt_input_load * standard_load all_inputs()
set_output_delay dflt_output_delay -clock clock all_outputs()
set_load dflt_output_load * standard_load all_outputs()
set_driving_cell -cell dflt_drive_cell -pin dflt_drive_pin all_inputs()
set_max_transition dflt_max_transition current_design
set_drive 0 clock
set_driving_cell -none clock
set_arrival 0 clock
set_drive 0 reset_l
set_driving_cell -none reset_l
set_input_delay 8 -clock clock reset_l
/************************************************************************/
/* Default operating conditions and environment */
/************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/************************************************************************/
/* Module specific timing constraints */
/************************************************************************/
set_driving_cell -cell ni01d5 { cbus_read_enable cbus_write_enable }
set_input_delay 5.0 -clock clock { cbus_read_enable }
set_input_delay 5.0 -clock clock { cbus_write_enable }
set_driving_cell -cell nt01d5 { cbus_data }
set_load 350 * standard_load { cbus_data }
set_input_delay 10.0 -clock clock { cbus_data }
set_output_delay 6.0 -clock clock { cbus_data }
set_driving_cell -cell ni01d7 { cbus_command cbus_select }
set_load 300 * standard_load { cbus_command cbus_select }
set_input_delay 2.0 -clock clock { cbus_command cbus_select }
set_max_fanout 10 * standard_load { cbus_command cbus_select }
set_load 0.5 { read_request }
/************************************************************************/
/* Check design before compile */
/************************************************************************/
check_design > module + ".lint"
/************************************************************************/
/* Compile */
/************************************************************************/
compile -map_effort high -ungroup_all
/************************************************************************/
/* Report results */
/************************************************************************/
include "report.dc"
report_constraint -all_violators
/************************************************************************/
/* Generate synthesis outputs */
/************************************************************************/
write -format edif -hierarchy -o module + ".edf" module
write -format verilog -hierarchy -o module + ".vsyn" module
write -format db -hierarchy -o module + ".db" module
quit