rspWrap_regression.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: rspWrap_regression.v,v 1.1.1.1 2002/05/17 06:14:58 blythe Exp $
// rspWrap_regression.v: the world outside the rsp, for regression tests
`timescale 1ns / 10ps
`include "rsp_regr.h"
module clock(clk);
output clk;
reg clk;
initial
#2 clk = 1;
always
#8 clk = ~ clk;
endmodule
module rspWrap();
reg reset_l;
reg iddq_test;
wire clk;
integer cycleCount;
integer i;
// DMA-related IO
reg frozen;
reg sp_cbus_read_enable;
reg sp_cbus_write_enable;
reg mem_cbus_write_enable; // *** Use for CPU read of mems
reg cmd_cbus_read_enable;
reg cmd_cbus_write_enable;
reg [1:0] cbus_select;
reg [2:0] cbus_command;
reg dma_start;
reg dma_last;
reg sp_dma_grant;
reg sp_read_grant;
reg cmd_dma_grant;
reg cmd_read_grant;
reg sp_dbus_read_enable;
reg sp_dbus_write_enable;
reg cbuf_ready;
reg cmd_busy; // DP CMDBUF is not empty
reg pipe_busy; // DP pipeline is active
reg tmem_busy; // DP TMEM is loading
wire [31:0] cbus_data;
wire [63:0] dbus_data;
wire [63:0] xbus_data;
wire sp_dma_request;
wire cmd_dma_request;
wire cmd_read_request;
wire sp_read_request;
wire mem_read_request;
wire cbuf_write;
task initDMA;
begin
frozen = 1'b0;
sp_cbus_read_enable = 1'b1;
sp_cbus_write_enable = 1'b0;
mem_cbus_write_enable = 1'b0;
cmd_cbus_read_enable = 1'b1;
cmd_cbus_write_enable = 1'b0;
cbus_select = 2'b0;
cbus_command = 3'b0;
dma_start = 0;
dma_last = 0;
sp_dma_grant = 0;
sp_read_grant = 0;
cmd_dma_grant = 0;
cmd_read_grant = 0;
sp_dbus_read_enable = 0;
sp_dbus_write_enable = 0;
cbuf_ready = 0;
cmd_busy = 0;
pipe_busy = 0;
tmem_busy = 0;
end
endtask
task initSURFile;
begin
/*
for (i=0; i<32; i=i+1) begin
rsp.su.sudp.suRFile_i.mem[i] = i;
end
rsp.su.sudp.suRFile_i.mem[0] = 32'hb00b0094;
*/
end
endtask
task initVURFile;
begin
`ifdef NEWVU
`else
for (i=0; i<32; i=i+1) begin
`VR0path.mem[i] = i*16;
`VR1path.mem[i] = (i*16)+1;
`VR2path.mem[i] = (i*16)+2;
`VR3path.mem[i] = (i*16)+3;
`VR4path.mem[i] = (i*16)+4;
`VR5path.mem[i] = (i*16)+5;
`VR6path.mem[i] = (i*16)+6;
`VR7path.mem[i] = (i*16)+7;
end
`endif
end
endtask
task initIMem;
begin
$readmemh("idata", rsp.imem.ram_prim, 0);
end
endtask
// ddata 16 byte word is numbered MSB to LSB: ddata0, ddata1, ... ddata15
// dmem model 16 byte word is numbered MSB to LSB:
// high.prim7, high.prim6, ... high.prim0, low.prim7, ... low.prim0
task initDMem;
begin
$readmemh("d_0.dhex", rsp.dmemx2.dmemHigh.ram_prim7, 0);
$readmemh("d_1.dhex", rsp.dmemx2.dmemHigh.ram_prim6, 0);
$readmemh("d_2.dhex", rsp.dmemx2.dmemHigh.ram_prim5, 0);
$readmemh("d_3.dhex", rsp.dmemx2.dmemHigh.ram_prim4, 0);
$readmemh("d_4.dhex", rsp.dmemx2.dmemHigh.ram_prim3, 0);
$readmemh("d_5.dhex", rsp.dmemx2.dmemHigh.ram_prim2, 0);
$readmemh("d_6.dhex", rsp.dmemx2.dmemHigh.ram_prim1, 0);
$readmemh("d_7.dhex", rsp.dmemx2.dmemHigh.ram_prim0, 0);
$readmemh("d_8.dhex", rsp.dmemx2.dmemLow.ram_prim7, 0);
$readmemh("d_9.dhex", rsp.dmemx2.dmemLow.ram_prim6, 0);
$readmemh("d_a.dhex", rsp.dmemx2.dmemLow.ram_prim5, 0);
$readmemh("d_b.dhex", rsp.dmemx2.dmemLow.ram_prim4, 0);
$readmemh("d_c.dhex", rsp.dmemx2.dmemLow.ram_prim3, 0);
$readmemh("d_d.dhex", rsp.dmemx2.dmemLow.ram_prim2, 0);
$readmemh("d_e.dhex", rsp.dmemx2.dmemLow.ram_prim1, 0);
$readmemh("d_f.dhex", rsp.dmemx2.dmemLow.ram_prim0, 0);
end
endtask
clock clock(clk);
rsp rsp(
.clk (clk),
.reset_l (reset_l),
.iddq_test (iddq_test),
// DMA-related IO
.frozen (frozen),
.sp_cbus_read_enable (sp_cbus_read_enable),
.sp_cbus_write_enable (sp_cbus_write_enable),
.mem_cbus_write_enable (mem_cbus_write_enable),
.cmd_cbus_read_enable (cmd_cbus_read_enable),
.cmd_cbus_write_enable (cmd_cbus_write_enable),
.cbus_select (cbus_select),
.cbus_command (cbus_command),
.dma_start (dma_start),
.dma_last (dma_last),
.sp_dma_grant (sp_dma_grant),
.sp_read_grant (sp_read_grant),
.cmd_dma_grant (cmd_dma_grant),
.cmd_read_grant (cmd_read_grant),
.cbuf_ready (cbuf_ready),
.sp_dma_request (sp_dma_request),
.sp_read_request (sp_read_request),
.mem_read_request (mem_read_request),
.cmd_dma_request (cmd_dma_request),
.cmd_read_request (cmd_read_request),
.sp_dbus_read_enable (sp_dbus_read_enable),
.sp_dbus_write_enable (sp_dbus_write_enable),
.cbuf_write (cbuf_write),
.cbus_data (cbus_data),
.dbus_data (dbus_data),
.xbus_data (xbus_data)
);
initial begin
initDMA;
initSURFile;
initVURFile;
// initDMem;
// initIMem;
// $dumpvars;
reset_l = 0;
iddq_test = 0;
repeat (10) @(negedge clk);
reset_l = 1; // *** need setup time on reset_l!
end // initial
always @(posedge clk) begin
if (!reset_l) begin
cycleCount = 0;
end
else begin
cycleCount = cycleCount+1;
end
end
wire [11:0] su_rd_pc;
wire [11:0] vu_rd_pc;
`ifdef RSP_GATE
`else
assign su_rd_pc =
rsp.su.suctl.issue.su_inst_sel[0] ? {rsp.su.suctl.issue.sav_pc, 2'b00} :
rsp.su.suctl.issue.su_inst_sel[1] ? {rsp.su.suctl.issue.cur_rd_pc[11:3], 3'b000} :
rsp.su.suctl.issue.su_inst_sel[2] ? {rsp.su.suctl.issue.cur_rd_pc[11:3], 3'b100} :
/* rsp.su.suctl.issue.su_inst_sel[3] ? */ 12'b0;
assign vu_rd_pc =
rsp.su.suctl.issue.vu_inst_sel[0] ? {rsp.su.suctl.issue.sav_pc, 2'b00} :
rsp.su.suctl.issue.vu_inst_sel[1] ? {rsp.su.suctl.issue.cur_rd_pc[11:3], 3'b000} :
rsp.su.suctl.issue.vu_inst_sel[2] ? {rsp.su.suctl.issue.cur_rd_pc[11:3], 3'b100} :
/* rsp.su.suctl.issue.vu_inst_sel[3] ? */ 12'b0;
/*
always @(negedge clk) begin
$write("time: %0t, pc: %h, broke: %h, kill: %h\n",
$time, {rsp.su.suctl.pc, 2'b0}, rsp.su.suctl.rd_broke,
rsp.su.suctl.kill_re_l);
if (rsp.su.suctl.rd_broke_k) begin
$write("time: %0t, su_inst: %h\n", $time, rsp.su.suctl.su_inst);
#100;
$write("later time: %0t, su_inst: %h\n",$time,rsp.su.suctl.su_inst);
$finish(2);
end
end
*/
`endif
endmodule