sudp_sc.ss
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/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = sudp_sc
wire_load = 256000
standard_load = 0.01
clock = clk
default_input_delay = 1.5
default_output_delay = 1.0
default_input_load = 20
default_output_load = 20
default_drive_cell = dfntnh
default_drive_pin = q
/*****************************************************************************/
/* set the path and read */
/*****************************************************************************/
search_path = {. \
/ecad/synopsys/current/libraries/syn \
/ecad/reality/lib/synopsys/nec35_v2.1 \
/ecad/reality/lib/synopsys/rcp_lib \
../src };
read -f verilog ../src/sudp_rf.v
read -f verilog ../src/sudp_reg.v
read -f verilog ../src/sudp_mx21.v
read -f verilog ../src/sudp_mx41.v
read -f verilog ../src/sudp_mx81.v
read -f verilog ../src/sudp_tri.v
read -f verilog ../src/sudp_shift.v
read -f verilog ../src/sudp_eq.v
read -f verilog ../src/sudp_comp.v
read -f verilog ../src/sudp_latg.v
read -f verilog ../src/sudp_mode.v
read -f verilog ../src/sudp_nand.v
read -f verilog ../src/sudp_add32.v
read -f verilog ../src/sudp_alu.v
read -f verilog ../src/sudp_buf.v
read -f verilog ../src/sudp_sc.v
current_design = module
/*****************************************************************************/
/* default environment */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/*****************************************************************************/
/* default constraint */
/*****************************************************************************/
/* set_max_area 0 */
set_dont_touch { ne35hd130d/nt01d* }
create_clock clock -period 16.0 -waveform {0.0 8.0}
set_input_delay default_input_delay -clock clock all_inputs()
set_output_delay default_output_delay -clock clock all_outputs()
set_load default_output_load * standard_load all_outputs()
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs()
/*****************************************************************************/
/* clock and reset constraints */
/*****************************************************************************/
set_drive 0 clock
set_arrival 0 clock
set_dont_touch_network clock
set_fix_hold all_clocks()
/*****************************************************************************/
/* custom constraints */
/*****************************************************************************/
set_max_transition 2.0 module
include module + ".con"
/*****************************************************************************/
/* check */
/*****************************************************************************/
check_design > module + ".lint"
/*****************************************************************************/
/* compile */
/*****************************************************************************/
ungroup -flatten -all
report_area
report -reference
report_constraint -all_violators > "report." + module + ".viol"
report_timing -path full -from *sltlt* -to {sushvamt} -nets -max_paths 50 >> "report." + module + ".viol"
report_timing -to all_outputs() -nets -max_paths 500 > "report." + module + ".output"
report_timing -from all_inputs() -nets -max_paths 500 > "report." + module + ".input"
write -format edif -hierarchy -o module + ".edf" module
write -format verilog -hierarchy -o module + ".vsyn" module
write -format db -hierarchy -o module + ".db" module
quit