rcp.ss
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/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = "rcp"
wire_load = 256000
clocks = { "clock" "gclk" }
standard_load = 0.01
default_input_delay = 1.5
default_output_delay = 14.0
default_input_load = 20
default_output_load = 20
default_drive_cell = "dfntnh"
default_drive_pin = "q"
default_period = 16.0
default_max_transition = 1.5
default_uncertainty = 1.0
/*****************************************************************************/
/* set the path and read */
/*****************************************************************************/
search_path = search_path + ".." + "../inc"
read -format edif ai/syn/ai.edf
read -format edif ar/syn/arb.edf
read -format edif at/syn/at.edf
read -format edif bl/syn/bl.edf
read -format edif cc/syn/cc.edf
read -format edif cs/syn/cs.edf
read -format edif cv/syn/cv.edf
read -format edif ep/syn/ep.edf
read -format edif ew/syn/ew.edf
read -format edif io/syn/io_cmd_dma.edf
read -format edif io/syn/io_mem_dma.edf
read -format edif ls/syn/ls.edf
read -format edif mi/syn/mi.edf
read -format edif ms/syn/ms.edf
read -format edif pi/syn/pi.edf
read -format edif ri/syn/ri.edf
read -format edif sb/syn/rspbusses.edf
read -format edif si/syn/si.edf
read -format edif st/syn/st.edf
read -format edif su/syn/su.edf
read -format edif tc/syn/tc.edf
read -format edif tf/syn/tf.edf
read -format edif tm/syn/tm.edf
read -format edif tst/syn/tst.edf
read -format edif vi/syn/vi.edf
read -format edif vu/syn/vu.edf
read -format edif rsp/syn/rsp.edf
read -format edif rdp/syn/rdp.edf
read -format edif syn/pad.edf
read -format verilog src/rcp.v
current_design = module
check_design > module + ".lint"
link
/*****************************************************************************/
/* constraints */
/*****************************************************************************/
/*
create_clock { pad_0/IOpad014/cp pad_0/IOpad031/cp } -period 16 -waveform {0 8}
set_disable_timing find (cell data_unit/rsp_0/ls/lsdp/ls_data_driver/b*)
set_multicycle_path 2 -from find (cell bl_logic/rdp_0/at/atbl/dlat*)
set_multicycle_path 2 -from find (cell cc_logic/rdp_0/at/atcc/dlat*)
set_multicycle_path 2 -from find (cell memspan/rdp_0/at/atms/dlat*)
set_multicycle_path 2 -from find (cell cs_ew_cv/rdp_0/at/atew/dlat*)
set_multicycle_path 2 -from find (cell tc_logic/rdp_0/at/attc/dlat*)
*/
/*****************************************************************************/
/* reports */
/*****************************************************************************/
include report.dc
/*****************************************************************************/
/* write design */
/*****************************************************************************/
write -format db -hierarchy -o module + ".db" module
/* write out the entire hierarchy in one file */
write -format verilog -hierarchy -o module + ".vsyn" module
/* write out the top level in one file */
write -format edif -o module + ".edf" module
quit