tm_half.v 2.94 KB
/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/

// $Id: tm_half.v,v 1.1.1.1 2002/05/17 06:14:58 blythe Exp $

////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module:      tm_half
// description: wrapper for 4 tmems
//
// designer:    Tony DeLaurier
// date:        11/5/94
//
////////////////////////////////////////////////////////////////////////

module tm_half (gclk, iddq, ram0_addr, ram1_addr, ram2_addr, ram3_addr, 
                            ram0_web,  ram1_web,  ram2_web,  ram3_web, 
                            ram0_din,  ram1_din,  ram2_din,  ram3_din, 
                            ram0_dout, ram1_dout, ram2_dout, ram3_dout);

  input gclk;                   // RDP gated clock
  input iddq;                   // iddq mode enabled

  input [7:0] ram0_addr;        // address to ram (bnk0)
  input [7:0] ram1_addr;        // address to ram (bnk1)
  input [7:0] ram2_addr;        // address to ram (bnk2)
  input [7:0] ram3_addr;        // address to ram (bnk3)

  input ram0_web;               // web to ram (bnk0)
  input ram1_web;               // web to ram (bnk1)
  input ram2_web;               // web to ram (bnk2)
  input ram3_web;               // web to ram (bnk3)

  input [15:0] ram0_din;        // data_in to ram (bnk0)
  input [15:0] ram1_din;        // data_in to ram (bnk1)
  input [15:0] ram2_din;        // data_in to ram (bnk2)
  input [15:0] ram3_din;        // data_in to ram (bnk3)

  output [15:0] ram0_dout;      // data_out from ram (bnk0)
  output [15:0] ram1_dout;      // data_out from ram (bnk1)
  output [15:0] ram2_dout;      // data_out from ram (bnk2)
  output [15:0] ram3_dout;      // data_out from ram (bnk3)

  tmem bnk0 (.pcg(gclk), .csb(iddq), .web({2{ram0_web}}), .a(ram0_addr),
              .di(ram0_din), .dout(ram0_dout));

  tmem bnk1 (.pcg(gclk), .csb(iddq), .web({2{ram1_web}}), .a(ram1_addr),
              .di(ram1_din), .dout(ram1_dout));

  tmem bnk2 (.pcg(gclk), .csb(iddq), .web({2{ram2_web}}), .a(ram2_addr),
              .di(ram2_din), .dout(ram2_dout));

  tmem bnk3 (.pcg(gclk), .csb(iddq), .web({2{ram3_web}}), .a(ram3_addr),
              .di(ram3_din), .dout(ram3_dout));

endmodule // tm_half