tm_mux1.v
14.1 KB
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/**************************************************************************
* *
* Copyright (C) 1995, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: tm_mux1.v,v 1.1.1.1 2002/05/17 06:14:58 blythe Exp $
////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: tm_mux1
// description: address-swap muxes, texel-sort muxes,
// color-index format muxes.
//
// designer: Tony DeLaurier
// date: 4/5/95
//
////////////////////////////////////////////////////////////////////////
module tm_mux1 (gclk, swap_rg, swap_ba, adrs_a, adrs_b_ba, adrs_c, adrs_d_ba,
adrs_b_rg, adrs_d_rg, dout_bnk0l, dout_bnk1l, dout_bnk2l,
dout_bnk3l, dout_bnk0h, dout_bnk1h, dout_bnk2h, dout_bnk3h,
tlut_en, tile_tex_size, palette,
//
sort_tex_a_low_buf, sort_tex_b_low_buf, sort_tex_c_low_buf, sort_tex_d_low_buf,
sort_tex_a_high_buf, sort_tex_b_high_buf, sort_tex_c_high_buf, sort_tex_d_high_buf,
swap_a_low_buf, swap_b_low_buf, swap_c_low_buf, swap_d_low_buf,
swap_a_high_buf, swap_b_high_buf, swap_c_high_buf, swap_d_high_buf,
clr_ind_a_buf, clr_ind_b_buf, clr_ind_c_buf, clr_ind_d_buf,
tile_tex_size_2d_buf, palette_1d_buf, tlut_en_2d_buf);
`include "tex.vh"
input gclk; // RDP gated clock
input swap_rg; // swap texels (RG)
input swap_ba; // swap texels (BA)
input [4:0] adrs_a; // address of texel a <12,3:0>
input [4:0] adrs_b_ba; // address of texel b (ba banks) <12,3:0>
input [4:0] adrs_c; // address of texel c <12,3:0>
input [4:0] adrs_d_ba; // address of texel d (ba banks) <12,3:0>
input [4:0] adrs_b_rg; // address of texel b (rg banks) <12,3:0>
input [4:0] adrs_d_rg; // address of texel d (rg banks) <12,3:0>
input [15:0] dout_bnk0l; // data out bank0 - low half
input [15:0] dout_bnk1l; // data out bank1 - low half
input [15:0] dout_bnk2l; // data out bank2 - low half
input [15:0] dout_bnk3l; // data out bank3 - low half
input [15:0] dout_bnk0h; // data out bank0 - high half
input [15:0] dout_bnk1h; // data out bank1 - high half
input [15:0] dout_bnk2h; // data out bank2 - high half
input [15:0] dout_bnk3h; // data out bank3 - high half
input tlut_en; // enable texture lookup table
input [1:0] tile_tex_size; // tile texel size
input [3:0] palette; // palette for 4-bit color index
output [15:0] sort_tex_a_low_buf; // sorted texel a (low half)
output [15:0] sort_tex_b_low_buf; // sorted texel b (low half)
output [15:0] sort_tex_c_low_buf; // sorted texel c (low half)
output [15:0] sort_tex_d_low_buf; // sorted texel d (low half)
output [15:0] sort_tex_a_high_buf;// sorted texel a (high half)
output [15:0] sort_tex_b_high_buf;// sorted texel b (high half)
output [15:0] sort_tex_c_high_buf;// sorted texel c (high half)
output [15:0] sort_tex_d_high_buf;// sorted texel d (high half)
output [4:0] swap_a_low_buf; // swapped address a (low half)
output [4:0] swap_b_low_buf; // swapped address b (low half)
output [4:0] swap_c_low_buf; // swapped address c (low half)
output [4:0] swap_d_low_buf; // swapped address d (low half)
output [4:0] swap_a_high_buf; // swapped address a (high half)
output [4:0] swap_b_high_buf; // swapped address b (high half)
output [4:0] swap_c_high_buf; // swapped address c (high half)
output [4:0] swap_d_high_buf; // swapped address d (high half)
output [7:0] clr_ind_a_buf; // color index texel a
output [7:0] clr_ind_b_buf; // color index texel b
output [7:0] clr_ind_c_buf; // color index texel c
output [7:0] clr_ind_d_buf; // color index texel d
output [1:0] tile_tex_size_2d_buf;// tile texel size delayed 2
output [3:0] palette_1d_buf; // palette delayed 1
output tlut_en_2d_buf; // tlut_en delayed 2
wire [15:0] sort_tex_a_low, sort_tex_b_low, sort_tex_c_low, sort_tex_d_low;
wire [15:0] sort_tex_a_high, sort_tex_b_high, sort_tex_c_high, sort_tex_d_high;
wire [4:0] swap_a_low, swap_b_low, swap_c_low, swap_d_low;
wire [4:0] swap_a_high, swap_b_high, swap_c_high, swap_d_high;
wire [7:0] clr_ind_a, clr_ind_b, clr_ind_c, clr_ind_d;
reg [1:0] tile_tex_size_1d; // tile texel size delayed 1
reg [1:0] tile_tex_size_2d; // tile texel size delayed 2
reg [4:0] adrs_a_1d; // adrs_a delayed 2
reg [4:0] adrs_b_ba_1d; // adrs_b_ba delayed 2
reg [4:0] adrs_c_1d; // adrs_c delayed 2
reg [4:0] adrs_d_ba_1d; // adrs_d_ba delayed 2
reg [4:0] adrs_b_rg_1d; // adrs_b_rg delayed 2
reg [4:0] adrs_d_rg_1d; // adrs_d_rg delayed 2
reg swap_rg_1d; // swap_rg delayed 1
reg swap_ba_1d; // swap_ba delayed 1
reg [3:0] palette_1d; // palette delayed 1
reg tlut_en_1d; // tlut_en delayed 1
reg tlut_en_2d; // tlut_en delayed 2
// nibble select mux
function [3:0] nib_select;
input [15:0] tex_rg;
input [1:0] select;
begin
case (select[1:0])
2'b00: nib_select[3:0] = tex_rg[3:0];
2'b01: nib_select[3:0] = tex_rg[7:4];
2'b10: nib_select[3:0] = tex_rg[11:8];
2'b11: nib_select[3:0] = tex_rg[15:12];
default: nib_select[3:0] = 4'hx;
endcase
end
endfunction // nib_select
// texel-sort mux (low half)
function [15:0] tex_sort_low;
input [3:2] adrs;
input [15:0] dout_bnk0;
input [15:0] dout_bnk1;
input [15:0] dout_bnk2;
input [15:0] dout_bnk3;
begin
case (adrs[3:2])
2'b00: tex_sort_low = dout_bnk0;
2'b01: tex_sort_low = dout_bnk1;
2'b10: tex_sort_low = dout_bnk2;
2'b11: tex_sort_low = dout_bnk3;
default: tex_sort_low = 16'hx;
endcase
end
endfunction // tex_sort_low
// texel-sort mux (high half)
function [15:0] tex_sort_high;
input [3:2] adrs;
input [1:0] tlut_bank;
input tlut_en;
input [15:0] dout_bnk0;
input [15:0] dout_bnk1;
input [15:0] dout_bnk2;
input [15:0] dout_bnk3;
reg [1:0] sel;
begin
sel[1:0] = tlut_en ? tlut_bank[1:0] : adrs[3:2];
case (sel[1:0])
2'b00: tex_sort_high = dout_bnk0;
2'b01: tex_sort_high = dout_bnk1;
2'b10: tex_sort_high = dout_bnk2;
2'b11: tex_sort_high = dout_bnk3;
default: tex_sort_high = 16'hx;
endcase
end
endfunction // tex_sort_high
// color index format mux
function [7:0] ci_form;
input [15:0] sort_tex;
input [1:0] swap_low;
input [1:0] tile_texel_size;
input [3:0] palette;
reg msb_sel;
reg [1:0] lsb_sel;
begin
msb_sel = ~swap_low[1];
case (tile_texel_size[1:0])
SIZE_4BIT:
lsb_sel[1:0] = ~swap_low[1:0];
default:
lsb_sel[1:0] = {~swap_low[1], 1'b0};
endcase
ci_form[7:4] = msb_sel ? sort_tex[15:12] : sort_tex[7:4];
ci_form[7:4] = (tile_texel_size == SIZE_4BIT) ? palette[3:0] :
ci_form[7:4];
ci_form[3:0] = nib_select(sort_tex[15:0], lsb_sel[1:0]);
end
endfunction // ci_form
always @(posedge gclk)
begin
// delay signals into block
tile_tex_size_1d <= tile_tex_size;
tile_tex_size_2d <= tile_tex_size_1d;
adrs_a_1d <= adrs_a;
adrs_b_ba_1d <= adrs_b_ba;
adrs_c_1d <= adrs_c;
adrs_d_ba_1d <= adrs_d_ba;
adrs_b_rg_1d <= adrs_b_rg;
adrs_d_rg_1d <= adrs_d_rg;
swap_rg_1d <= swap_rg;
swap_ba_1d <= swap_ba;
palette_1d <= palette;
tlut_en_1d <= tlut_en;
tlut_en_2d <= tlut_en_1d;
end // always
// address-swap muxes (low half)
assign swap_a_low[4:0] = (!swap_rg_1d) ? adrs_a_1d : adrs_d_rg_1d;
assign swap_b_low[4:0] = (!swap_rg_1d) ? adrs_b_rg_1d : adrs_c_1d;
assign swap_c_low[4:0] = (!swap_rg_1d) ? adrs_c_1d : adrs_b_rg_1d;
assign swap_d_low[4:0] = (!swap_rg_1d) ? adrs_d_rg_1d : adrs_a_1d;
// address-swap muxes (high half)
assign swap_a_high[4:0] = (!swap_ba_1d) ? adrs_a_1d : adrs_d_ba_1d;
assign swap_b_high[4:0] = (!swap_ba_1d) ? adrs_b_ba_1d : adrs_c_1d;
assign swap_c_high[4:0] = (!swap_ba_1d) ? adrs_c_1d : adrs_b_ba_1d;
assign swap_d_high[4:0] = (!swap_ba_1d) ? adrs_d_ba_1d : adrs_a_1d;
// texel-sort muxes (low half)
assign sort_tex_a_low[15:0] = tex_sort_low(swap_a_low[3:2], dout_bnk0l,
dout_bnk1l, dout_bnk2l, dout_bnk3l);
assign sort_tex_b_low[15:0] = tex_sort_low(swap_b_low[3:2], dout_bnk0l,
dout_bnk1l, dout_bnk2l, dout_bnk3l);
assign sort_tex_c_low[15:0] = tex_sort_low(swap_c_low[3:2], dout_bnk0l,
dout_bnk1l, dout_bnk2l, dout_bnk3l);
assign sort_tex_d_low[15:0] = tex_sort_low(swap_d_low[3:2], dout_bnk0l,
dout_bnk1l, dout_bnk2l, dout_bnk3l);
// texel-sort muxes (high half)
assign sort_tex_a_high[15:0] = tex_sort_high(swap_a_high[3:2], 2'b00,
tlut_en_2d, dout_bnk0h, dout_bnk1h,
dout_bnk2h, dout_bnk3h);
assign sort_tex_b_high[15:0] = tex_sort_high(swap_b_high[3:2], 2'b01,
tlut_en_2d, dout_bnk0h, dout_bnk1h,
dout_bnk2h, dout_bnk3h);
assign sort_tex_c_high[15:0] = tex_sort_high(swap_c_high[3:2], 2'b10,
tlut_en_2d, dout_bnk0h, dout_bnk1h,
dout_bnk2h, dout_bnk3h);
assign sort_tex_d_high[15:0] = tex_sort_high(swap_d_high[3:2], 2'b11,
tlut_en_2d, dout_bnk0h, dout_bnk1h,
dout_bnk2h, dout_bnk3h);
// color index format muxes
assign clr_ind_a[7:0] = ci_form(sort_tex_a_low, swap_a_low[1:0],
tile_tex_size_2d, palette_1d);
assign clr_ind_b[7:0] = ci_form(sort_tex_b_low, swap_b_low[1:0],
tile_tex_size_2d, palette_1d);
assign clr_ind_c[7:0] = ci_form(sort_tex_c_low, swap_c_low[1:0],
tile_tex_size_2d, palette_1d);
assign clr_ind_d[7:0] = ci_form(sort_tex_d_low, swap_d_low[1:0],
tile_tex_size_2d, palette_1d);
tm_mux1_buf16 u_sort_tex_a_low(.z(sort_tex_a_low_buf), .i(sort_tex_a_low));
tm_mux1_buf16 u_sort_tex_b_low(.z(sort_tex_b_low_buf), .i(sort_tex_b_low));
tm_mux1_buf16 u_sort_tex_c_low(.z(sort_tex_c_low_buf), .i(sort_tex_c_low));
tm_mux1_buf16 u_sort_tex_d_low(.z(sort_tex_d_low_buf), .i(sort_tex_d_low));
tm_mux1_buf16 u_sort_tex_a_high(.z(sort_tex_a_high_buf), .i(sort_tex_a_high));
tm_mux1_buf16 u_sort_tex_b_high(.z(sort_tex_b_high_buf), .i(sort_tex_b_high));
tm_mux1_buf16 u_sort_tex_c_high(.z(sort_tex_c_high_buf), .i(sort_tex_c_high));
tm_mux1_buf16 u_sort_tex_d_high(.z(sort_tex_d_high_buf), .i(sort_tex_d_high));
tm_mux1_buf5 u_swap_a_low(.z(swap_a_low_buf), .i(swap_a_low));
tm_mux1_buf5 u_swap_b_low(.z(swap_b_low_buf), .i(swap_b_low));
tm_mux1_buf5 u_swap_c_low(.z(swap_c_low_buf), .i(swap_c_low));
tm_mux1_buf5 u_swap_d_low(.z(swap_d_low_buf), .i(swap_d_low));
tm_mux1_buf5 u_swap_a_high(.z(swap_a_high_buf), .i(swap_a_high));
tm_mux1_buf5 u_swap_b_high(.z(swap_b_high_buf), .i(swap_b_high));
tm_mux1_buf5 u_swap_c_high(.z(swap_c_high_buf), .i(swap_c_high));
tm_mux1_buf5 u_swap_d_high(.z(swap_d_high_buf), .i(swap_d_high));
tm_mux1_buf8 u_clr_ind_a(.z(clr_ind_a_buf), .i(clr_ind_a));
tm_mux1_buf8 u_clr_ind_b(.z(clr_ind_b_buf), .i(clr_ind_b));
tm_mux1_buf8 u_clr_ind_c(.z(clr_ind_c_buf), .i(clr_ind_c));
tm_mux1_buf8 u_clr_ind_d(.z(clr_ind_d_buf), .i(clr_ind_d));
ni01d5 u_tile_tex_size_2d0(.z(tile_tex_size_2d_buf[0]), .i(tile_tex_size_2d[0]));
ni01d5 u_tile_tex_size_2d1(.z(tile_tex_size_2d_buf[1]), .i(tile_tex_size_2d[1]));
ni01d5 u_palette_1d0(.z(palette_1d_buf[0]), .i(palette_1d[0]));
ni01d5 u_palette_1d1(.z(palette_1d_buf[1]), .i(palette_1d[1]));
ni01d5 u_palette_1d2(.z(palette_1d_buf[2]), .i(palette_1d[2]));
ni01d5 u_palette_1d3(.z(palette_1d_buf[3]), .i(palette_1d[3]));
ni01d5 u_tlut_en_2d(.z(tlut_en_2d_buf), .i(tlut_en_2d));
endmodule // tm_mux1
// d5 buffer x 16
module tm_mux1_buf16 (i, z);
input [15:0] i;
output [15:0] z;
ni01d5 u_buf00(.z(z[ 0]), .i(i[ 0]));
ni01d5 u_buf01(.z(z[ 1]), .i(i[ 1]));
ni01d5 u_buf02(.z(z[ 2]), .i(i[ 2]));
ni01d5 u_buf03(.z(z[ 3]), .i(i[ 3]));
ni01d5 u_buf04(.z(z[ 4]), .i(i[ 4]));
ni01d5 u_buf05(.z(z[ 5]), .i(i[ 5]));
ni01d5 u_buf06(.z(z[ 6]), .i(i[ 6]));
ni01d5 u_buf07(.z(z[ 7]), .i(i[ 7]));
ni01d5 u_buf08(.z(z[ 8]), .i(i[ 8]));
ni01d5 u_buf09(.z(z[ 9]), .i(i[ 9]));
ni01d5 u_buf10(.z(z[10]), .i(i[10]));
ni01d5 u_buf11(.z(z[11]), .i(i[11]));
ni01d5 u_buf12(.z(z[12]), .i(i[12]));
ni01d5 u_buf13(.z(z[13]), .i(i[13]));
ni01d5 u_buf14(.z(z[14]), .i(i[14]));
ni01d5 u_buf15(.z(z[15]), .i(i[15]));
endmodule
// d5 buffer x 8
module tm_mux1_buf8 (i, z);
input [7:0] i;
output [7:0] z;
ni01d5 u_buf00(.z(z[ 0]), .i(i[ 0]));
ni01d5 u_buf01(.z(z[ 1]), .i(i[ 1]));
ni01d5 u_buf02(.z(z[ 2]), .i(i[ 2]));
ni01d5 u_buf03(.z(z[ 3]), .i(i[ 3]));
ni01d5 u_buf04(.z(z[ 4]), .i(i[ 4]));
ni01d5 u_buf05(.z(z[ 5]), .i(i[ 5]));
ni01d5 u_buf06(.z(z[ 6]), .i(i[ 6]));
ni01d5 u_buf07(.z(z[ 7]), .i(i[ 7]));
endmodule
// d5 buffer x 5
module tm_mux1_buf5 (i, z);
input [4:0] i;
output [4:0] z;
ni01d5 u_buf00(.z(z[ 0]), .i(i[ 0]));
ni01d5 u_buf01(.z(z[ 1]), .i(i[ 1]));
ni01d5 u_buf02(.z(z[ 2]), .i(i[ 2]));
ni01d5 u_buf03(.z(z[ 3]), .i(i[ 3]));
ni01d5 u_buf04(.z(z[ 4]), .i(i[ 4]));
endmodule