/* read the verilog sources */
read -f verilog ../src/tm_half.v

current_design = tm_half

max_area 0

link 

check_design > tm_half.lint

compile_no_new_cells_at_top_level = "true"
compile -map_effort low 

report -reference

write -f edif -o tm_half.edf -hier tm_half

quit