vi_divot.v 2.84 KB
/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/

// $Id: vi_divot.v,v 1.1.1.1 2002/05/17 06:14:58 blythe Exp $

////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module:	vi_divot
// description:	Divot correction for video interface.
//
// designer:	Phil Gossett
// date:	1/9/95
//
////////////////////////////////////////////////////////////////////////

module vi_divot (vclk, type, divot_enable,
		rgb, cvg, sync, divot_rgb, divot_sync);

input vclk;
input [1:0] type;	// 0 means blank
input divot_enable;
input [7:0] rgb;
input [2:0] cvg;
input sync;

output [7:0] divot_rgb;
output divot_sync;

wire [7:0] median;
wire [7:0] rgb_a;
wire [2:0] cvg_a;
wire sync_a;
wire hold;

reg hold_reg;
reg [7:0] rgb_p;
reg [7:0] rgb_q;
reg [7:0] rgb_r;
reg [7:0] rgb_b;
reg [7:0] rgb_s;
reg [7:0] rgb_t;
reg [7:0] rgb_u;
reg [7:0] rgb_c;
reg [2:0] cvg_b;
reg [2:0] cvg_c;
reg sync_p;
reg sync_q;
reg sync_r;
reg sync_b;
reg sync_s;
reg sync_t;
reg sync_u;
reg sync_c;
reg [7:0] divot_rgb;
reg divot_sync;

assign rgb_a  = rgb;
assign cvg_a  = cvg;
assign sync_a = sync;

always @(posedge vclk)
begin
	rgb_p[7]    <= (hold && (| type)) ? rgb_b[7]   : rgb_a[7];
	rgb_p[6:0]  <= (hold && !sync_a ) ? rgb_b[6:0] : rgb_a[6:0];
	rgb_q  <= rgb_p;
	rgb_r  <= rgb_q;
	rgb_b  <= rgb_r;
	rgb_s[7]    <= (hold && (| type)) ? rgb_c[7]   : rgb_b[7];
	rgb_s[6:0]  <= (hold && !sync_b ) ? rgb_c[6:0] : rgb_b[6:0];
	rgb_t  <= rgb_s;
	rgb_u  <= rgb_t;
	rgb_c  <= rgb_u;

	cvg_b  <= (!hold_reg & sync_b) ? cvg_a : cvg_b;
	cvg_c  <= (!hold_reg & sync_c) ? cvg_b : cvg_c;

	sync_p <= sync_a;
	sync_q <= sync_p;
	sync_r <= sync_q;
	sync_b <= sync_r;
	sync_s <= sync_b;
	sync_t <= sync_s;
	sync_u <= sync_t;
	sync_c <= sync_u;
end

vi_divot_median vimed (.a(rgb_a), .b(rgb_b), .c(rgb_c), .z(median));
assign hold = sync_a ? rgb_a[6] : hold_reg;

always @(posedge vclk)
begin
	hold_reg <= hold;
	divot_rgb <= sync_a ? {(rgb_a[7] || rgb_b[7] || rgb_c[7]),
					rgb_a[6:0]} :
			      ((!divot_enable || (& {cvg_a,cvg_b,cvg_c})) ?
					rgb_b :
					median);
	divot_sync <= sync_a;
end

endmodule // vi_divot