/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/

// $Id: vi_sync.v,v 1.1.1.1 2002/05/17 06:14:58 blythe Exp $

////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module:	vi_sync
// description:	Sync generator and rgba unpacker for video interface.
//
// designer:	Phil Gossett
// date:	1/3/95
//
////////////////////////////////////////////////////////////////////////

module vi_sync (vclk, reset_l,
	type, serrate, aa_mode, pixel_adv,
	origin, width, v_int, hsync_width,
	burst_width, vsync_width, burst_start, v_sync_period,
	h_sync_period, leap_pattern, hsync_leap_b, hsync_leap_a,
	h_video_end, h_video_start, v_video_end, v_video_start,
	v_burst_end, v_burst_start, x_scale, y_scale, x_offset, y_offset,
	data_a, data_b, block_partial, block_grant,
	block_address, block_length, block_word,
	bank_sel, block_start, block_count,
	read_addr, pre_int, horizontal_flag,
	hfrac, vfrac, v_current,
	rgb0i, rgb1i, rgb2i, rgb3i,
	cvg0i, cvg1i, cvg2i, cvg3i,
	synci);

input vclk;
input reset_l;
input [1:0] type;
input serrate;
input [1:0] aa_mode;
input [3:0] pixel_adv;
input [23:0] origin;
input [11:0] width;
input [9:0] v_int;
input [7:0] hsync_width;
input [7:0] burst_width;
input [3:0] vsync_width;
input [9:0] burst_start;
input [9:0] v_sync_period;
input [11:0] h_sync_period;
input [4:0] leap_pattern;
input [11:0] hsync_leap_b;
input [11:0] hsync_leap_a;
input [9:0] h_video_end;
input [9:0] h_video_start;
input [9:0] v_video_end;
input [9:0] v_video_start;
input [9:0] v_burst_end;
input [9:0] v_burst_start;
input [11:0] x_scale;
input [11:0] y_scale;
input [11:0] x_offset;
input [11:0] y_offset;
input [71:0] data_a;
input [71:0] data_b;
input block_partial;			// some partially covered
input block_grant;

output [23:0] block_address;		// address of requested block
output [6:0] block_length;		// length of requested block
output [3:0] block_word;		// location in buffer
output bank_sel;			// buffer bank select
output block_start;			// consecutive req's
output [1:0] block_count;		// number of consecutive req's - 1
output [3:0] read_addr;
output pre_int;
output horizontal_flag;
output [4:0] hfrac;
output [4:0] vfrac;
output [9:0] v_current;
output [7:0] rgb0i;
output [7:0] rgb1i;
output [7:0] rgb2i;
output [7:0] rgb3i;
output [2:0] cvg0i;
output [2:0] cvg1i;
output [2:0] cvg2i;
output [2:0] cvg3i;
output synci;

// outputs
reg [23:0] block_address;
reg [6:0] block_length;
reg [3:0] block_word;
reg bank_sel;
reg block_start;
reg [1:0] block_count;
reg [3:0] read_addr;
reg pre_int;
reg [7:0] rgb0i;
reg [7:0] rgb1i;
reg [7:0] rgb2i;
reg [7:0] rgb3i;
reg [2:0] cvg0i;
reg [2:0] cvg1i;
reg [2:0] cvg2i;
reg [2:0] cvg3i;
reg synci;

wire block_partial_1d;	// instanciated synchronizer delay
wire block_partial_2d;
wire block_partial_3d;
wire block_grant_1d;
wire block_grant_2d;
wire block_grant_3d;

reg block_grant_4d;
reg horizontal_flag_1d;	// delay line
reg horizontal_flag_2d;
reg horizontal_flag_3d;
reg horizontal_flag_4d;
reg [26:0] rgba_2d;
reg [26:0] rgba_3d;
reg [26:0] rgba_4d;
reg [26:3] rgba_5d;
reg [18:3] rgba_6d;
reg [10:3] rgba_7d;
reg [4:0] last_lsbs;
reg [1:0] span_sel_1d;
reg [1:0] span_sel_2d;
reg [1:0] span_sel_3d;
reg [1:0] span_sel_4d;
reg [1:0] span_sel_5d;
reg [7:0] pixel_sync_1d;
reg [7:0] pixel_sync_2d;
reg [7:0] pixel_sync_3d;
reg [15:0] block_delta;

wire [1:0] span_sel;
wire [6:0] pixel_addr;
wire [23:0] pre_block_addr;
wire [23:0] block_addr;
wire [1:0] block_sel;
wire [7:0] pixel_sync;
wire h_blank_flag;
wire a_blank_flag;
wire p_blank_flag;
wire v_blank_flag;
wire [9:0] pre_hfrac;
wire [9:0] pre_vfrac;
wire vfrac_zero;
wire [71:0] data_ab;
wire [26:0] rgba;
wire [23:0] byte_width;

vi_sync_fsm vifsm  (.vclk(vclk), .reset_l(reset_l),
	.type(type), .serrate(serrate), .aa_mode(aa_mode),
	.pixel_adv(pixel_adv), .origin(origin), .width(width),
	.hsync_width(hsync_width), .burst_width(burst_width),
	.vsync_width(vsync_width), .burst_start(burst_start),
	.v_sync_period(v_sync_period), .h_sync_period(h_sync_period),
	.leap_pattern(leap_pattern),
	.hsync_leap_b(hsync_leap_b), .hsync_leap_a(hsync_leap_a),
	.h_video_end(h_video_end), .h_video_start(h_video_start),
	.v_video_end(v_video_end), .v_video_start(v_video_start),
	.v_burst_end(v_burst_end), .v_burst_start(v_burst_start),
	.x_scale(x_scale), .y_scale(y_scale),
	.x_offset(x_offset), .y_offset(y_offset),

	.block_addr(block_addr),
	.hfrac(pre_hfrac), .vfrac(pre_vfrac), .v_current(v_current),
	.span_sel(span_sel), .pixel_addr(pixel_addr),
	.pixel_sync(pixel_sync), .horizontal_flag(horizontal_flag),
	.h_blank_flag(h_blank_flag), .a_blank_flag(a_blank_flag),
	.p_blank_flag(p_blank_flag), .v_blank_flag(v_blank_flag));

assign hfrac = (aa_mode == 3) ? 0 : pre_hfrac[9:5];
assign vfrac = (aa_mode == 3) ? 0 : pre_vfrac[9:5];
assign vfrac_zero = (pre_vfrac == 0);
assign block_sel = {span_sel[1], (span_sel[1] ^~ span_sel[0])};
assign data_ab = bank_sel ? data_a : data_b;
assign rgba    = !type[1] ?
			 27'h7 :
			 (!type[0] ? (!pixel_addr[1] ? (!pixel_addr[0] ?
						{data_ab[71:67], 3'b0,
						 data_ab[66:62], 3'b0,
						 data_ab[61:57], 3'b0,
						 data_ab[56:54]} :
						{data_ab[53:49], 3'b0,
						 data_ab[48:44], 3'b0,
						 data_ab[43:39], 3'b0,
						 data_ab[38:36]}) :
						       (!pixel_addr[0] ?
						{data_ab[35:31], 3'b0,
						 data_ab[30:26], 3'b0,
						 data_ab[25:21], 3'b0,
						 data_ab[20:18]} :
						{data_ab[17:13], 3'b0,
						 data_ab[12:8],  3'b0,
						 data_ab[7:3],   3'b0,
						 data_ab[2:0]})) :
				     (!pixel_addr[0] ?
					{data_ab[71:64],
					 data_ab[63:56],
					 data_ab[53:46],
					 data_ab[45:43]} :
					{data_ab[35:28],
					 data_ab[27:20],
					 data_ab[17:10],
					 data_ab[9:7]}));
assign byte_width = !type[0] ? {width,1'b0} : {width,2'b0};
assign pre_block_addr = block_addr - 8;

reg [23:0] pre_block_address;
always @(block_address or block_delta) begin : pba_block
	/* synopsys resource pba_res:
	map_to_module = "DW01_add",
	implementation = "cla",
	ops = "ba";
	*/

	pre_block_address = block_address
	   + {{8{block_delta[15]}}, block_delta[15:0]}; // synopsys label ba
	end


always @(posedge vclk)
begin
	read_addr <= !aa_mode[1] ? (!type[0] ?
					{block_sel,pixel_addr[3:2]} :
					{block_sel,pixel_addr[2:1]}) :
			(!aa_mode[0] ?
				   (!type[0] ?
					{span_sel[1],pixel_addr[4:2]} :
					{span_sel[1],pixel_addr[3:1]}) :
				   (!type[0] ?
					pixel_addr[5:2] :
					pixel_addr[4:1]));
	bank_sel <= (!aa_mode[1] ? (!type[0] ?
					pixel_addr[4] :
					pixel_addr[3]) :
			(!aa_mode[0] ?
				   (!type[0] ?
					pixel_addr[5] :
					pixel_addr[4]) :
				   (!type[0] ?
					pixel_addr[6] :
					pixel_addr[5]))) ^ h_blank_flag;

	span_sel_1d <= span_sel;
	span_sel_2d <= span_sel_1d;
	span_sel_3d <= span_sel_2d;
	span_sel_4d <= span_sel_3d;
	span_sel_5d <= span_sel_4d;

	rgba_2d[26:0] <= rgba;
	rgba_3d[26:0] <= rgba_2d[26:0];
	rgba_4d[26:0] <= rgba_3d[26:0];
	rgba_5d[26:3] <= rgba_4d[26:3];
	rgba_6d[18:3] <= rgba_5d[18:3];
	rgba_7d[10:3] <= rgba_6d[10:3];

        pixel_sync_1d <= pixel_sync;
        pixel_sync_2d <= pixel_sync_1d;
        pixel_sync_3d <= pixel_sync_2d;

	rgb0i <= !span_sel_5d[1] ? (!span_sel_5d[0] ?	rgba_5d[26:19] : 
							rgba_6d[18:11]) :
				   (!span_sel_5d[0] ?	rgba_7d[10:3] :
							pixel_sync_3d);
	rgb1i <= !span_sel_5d[1] ? (!span_sel_5d[0] ?	rgba_4d[26:19] : 
							rgba_5d[18:11]) :
				   (!span_sel_5d[0] ?	rgba_6d[10:3] :
							pixel_sync_3d);
	rgb2i <= !span_sel_5d[1] ? (!span_sel_5d[0] ?	rgba_3d[26:19] : 
							rgba_4d[18:11]) :
				   (!span_sel_5d[0] ?	rgba_5d[10:3] :
							pixel_sync_3d);
	rgb3i <= !span_sel_5d[1] ? (!span_sel_5d[0] ?	rgba_2d[26:19] : 
							rgba_3d[18:11]) :
				   (!span_sel_5d[0] ?	rgba_4d[10:3] :
							pixel_sync_3d);

	cvg0i <= rgba_4d[2:0];
	cvg1i <= rgba_3d[2:0];
	cvg2i <= rgba_2d[2:0];
	cvg3i <= rgba[2:0];

	synci <= (span_sel_5d == 3);
end

// instanciated synchronizer flops
dfntnb bpsy1 (.cp(vclk), .d(block_partial),    .q(block_partial_1d));
dfntnb bpsy2 (.cp(vclk), .d(block_partial_1d), .q(block_partial_2d));
dfntnb bpsy3 (.cp(vclk), .d(block_partial_2d), .q(block_partial_3d));
dfntnb dgsy1 (.cp(vclk), .d(block_grant),    .q(block_grant_1d));
dfntnb dgsy2 (.cp(vclk), .d(block_grant_1d), .q(block_grant_2d));
dfntnb dgsy3 (.cp(vclk), .d(block_grant_2d), .q(block_grant_3d));

// state machine
reg [2:0] state;
parameter
        STATE_LINE_A	     = 0,
        STATE_LINE_B         = 1,
        STATE_LINE_U         = 2,
        STATE_LINE_D         = 3,
        STATE_PRE_IDLE       = 4,
        STATE_IDLE           = 5,
        STATE_PRE_WAIT       = 6,
        STATE_WAIT           = 7;

parameter
        FRAC_ALWAYS	     = 0,
        FRAC_BYNEED          = 1,
        FRAC_NEVER           = 2,
        FRAC_PIXEL           = 3,
        INT_ALWAYS	     = 4,
        INT_BYNEED           = 5,
        INT_NEVER            = 6,
        INT_PIXEL            = 7;

always @(posedge vclk or negedge reset_l)
   begin
   if (!reset_l)
      begin
      // resetable registers
      horizontal_flag_4d <= 0;
      last_lsbs <= 0;
      block_start <= 0;
      pre_int <= 0;
      state <= STATE_IDLE;
      block_address <= 0;
      block_length <= 0;
      block_word <= 0;
      block_count <= 0;
      block_grant_4d <= 0;
      horizontal_flag_1d <= 0;
      horizontal_flag_2d <= 0;
      horizontal_flag_3d <= 0;
      block_delta <= 0;
      end
   else
      begin
      pre_int <= (v_int == v_current);
      block_grant_4d <= block_grant_3d;
      horizontal_flag_1d <= horizontal_flag;
      horizontal_flag_2d <= horizontal_flag_1d;
      horizontal_flag_3d <= horizontal_flag_2d;
      case ({vfrac_zero, aa_mode})
         FRAC_ALWAYS:
            begin
            case (state)
               STATE_WAIT,	// unused state (guarantees exit)
               STATE_IDLE :
                  begin
                  horizontal_flag_4d <= horizontal_flag_3d;
                  if (!v_blank_flag &&
                      (horizontal_flag_3d && !horizontal_flag_4d))
                     begin
                     last_lsbs <= block_addr[6:3];
                     block_start <= 1;
                     block_count <= 3;
                     block_address <= block_addr;
                     block_length <= 4*8-1;
                     block_word <= 0;
                     state <= STATE_LINE_A;
                     end
                  else
                     begin
                     if (!v_blank_flag && !p_blank_flag && !a_blank_flag &&
                         (block_addr[4:3] == last_lsbs[1:0]))
                        begin
                        block_start <= 1;
                        block_count <= 3;
                        block_word <= 0;
                        state <= STATE_LINE_A;
                        end
                     end
                  end
               STATE_LINE_A :
                  begin
                  block_delta <= byte_width;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_address <= pre_block_address;
                     block_word <= 8;
                     state <= STATE_LINE_B;
                     end
                  end
               STATE_LINE_B :
                  begin
                  block_delta <= byte_width;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_address <= pre_block_address;
                     block_word <= 12;
                     state <= STATE_LINE_D;
                     end
                  end
               STATE_LINE_D :
                  begin
                  block_delta <= -{byte_width,1'b0} - byte_width;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_address <= pre_block_address;
                     block_word <= 4;
                     state <= STATE_LINE_U;
                     end
                  end
               STATE_LINE_U :
                  begin
                  block_delta <= byte_width + 32;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_start <= 0;
                     block_address <= pre_block_address;
                     block_word <= 0;
                     if (p_blank_flag)
                        begin
                        state <= STATE_IDLE;
                        end
                     else
                        begin
                        state <= STATE_PRE_IDLE;
                        end
                     end
                  end
               STATE_PRE_WAIT,	// unused state (guarantees exit)
               STATE_PRE_IDLE :
                  begin
                  if (block_addr[4:3] != last_lsbs[1:0])
                     begin
                     state <= STATE_IDLE;
                     end
                  end
            endcase
            end
         FRAC_BYNEED:
            begin
            case (state)
               STATE_IDLE :
                  begin
                  horizontal_flag_4d <= horizontal_flag_3d;
                  if (!v_blank_flag &&
                      (horizontal_flag_3d && !horizontal_flag_4d))
                     begin
                     last_lsbs <= block_addr[6:3];
                     block_start <= 1;
                     block_count <= 1;
                     block_address <= pre_block_addr;
                     block_length <= 6*8-1;
                     block_word <= 15;
                     state <= STATE_LINE_A;
                     end
                  else
                     begin
                     if (!v_blank_flag && !p_blank_flag && !a_blank_flag &&
                         (block_addr[4:3] == last_lsbs[1:0]))
                        begin
                        block_start <= 1;
                        block_count <= 1;
                        block_length <= 6*8-1;
                        block_word <= 15;
                        state <= STATE_LINE_A;
                        end
                     end
                  end
               STATE_LINE_A :
                  begin
                  block_delta <= byte_width;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_address <= pre_block_address;
                     block_word <= 7;
                     state <= STATE_LINE_B;
                     end
                  end
               STATE_LINE_B :
                  begin
                  block_delta <= byte_width + 8;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_start <= 0;
                     block_count <= 1;
                     block_address <= pre_block_address;
                     block_length <= 4*8-1;
                     block_word <= 12;
                     if (p_blank_flag)
                        begin
                        state <= STATE_WAIT;
                        end
                     else
                        begin
                        state <= STATE_PRE_WAIT;
                        end
                     end
                  end
               STATE_PRE_WAIT :
                  begin
                  if (block_addr[4:3] != last_lsbs[1:0])
                     begin
                     state <= STATE_WAIT;
                     end
                  end
               STATE_WAIT :
                  begin
                  block_delta <= -{byte_width,1'b0} + 32 - 8;
                  if (block_partial_3d)
                     begin
                     block_start <= 1;
                     state <= STATE_LINE_D;
                     end
                  else
                     begin
                     horizontal_flag_4d <= horizontal_flag_3d;
                     if (!v_blank_flag &&
                         (horizontal_flag_3d && !horizontal_flag_4d))
                        begin
                        last_lsbs <= block_addr[6:3];
                        block_start <= 1;
                        block_count <= 1;
                        block_address <= pre_block_addr;
                        block_length <= 6*8-1;
                        block_word <= 15;
                        state <= STATE_LINE_A;
                        end
                     else
                        begin
                        if (!v_blank_flag && !p_blank_flag && !a_blank_flag &&
                            (block_addr[4:3] == last_lsbs[1:0]))
                           begin
                           block_start <= 1;
                           block_count <= 1;
                           block_address <= pre_block_address;
                           block_length <= 6*8-1;
                           block_word <= 15;
                           state <= STATE_LINE_A;
                           end
                        end
                     end
                  end
               STATE_LINE_D :
                  begin
                  block_delta <= -{byte_width,1'b0} - byte_width;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_address <= pre_block_address;
                     block_word <= 4;
                     state <= STATE_LINE_U;
                     end
                  end
               STATE_LINE_U :
                  begin
                  block_delta <= byte_width + 32 - 8;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_start <= 0;
                     block_address <= pre_block_address;
                     block_word <= 0;
                     if (p_blank_flag)
                        begin
                        state <= STATE_IDLE;
                        end
                     else
                        begin
                        state <= STATE_PRE_IDLE;
                        end
                     end
                  end
               STATE_PRE_IDLE :
                  begin
                  if (block_addr[4:3] != last_lsbs[1:0])
                     begin
                     state <= STATE_IDLE;
                     end
                  end
            endcase
            end
         FRAC_NEVER:
            begin
            case (state)
               STATE_WAIT,	// unused state (guarantees exit)
               STATE_IDLE :
                  begin
                  horizontal_flag_4d <= horizontal_flag_3d;
                  if (!v_blank_flag &&
                      (horizontal_flag_3d && !horizontal_flag_4d))
                     begin
                     last_lsbs <= block_addr[6:3];
                     block_start <= 1;
                     block_count <= 1;
                     block_address <= block_addr;
                     block_length <= 8*8-1;
                     block_word <= 0;
                     state <= STATE_LINE_A;
                     end
                  else
                     begin
                     if (!v_blank_flag && !p_blank_flag && !a_blank_flag &&
                         (block_addr[5:3] == last_lsbs[2:0]))
                        begin
                        block_start <= 1;
                        block_count <= 1;
                        block_word <= 0;
                        state <= STATE_LINE_A;
                        end
                     end
                  end
               STATE_LINE_A :
                  begin
                  block_delta <= byte_width;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_address <= pre_block_address;
                     block_word <= 8;
                     state <= STATE_LINE_B;
                     end
                  end
               STATE_LINE_U,	// unused state (guarantees exit)
               STATE_LINE_D,	// unused state (guarantees exit)
               STATE_LINE_B :
                  begin
                  block_delta <= -byte_width + 64;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_start <= 0;
                     block_address <= pre_block_address;
                     block_word <= 0;
                     if (p_blank_flag)
                        begin
                        state <= STATE_IDLE;
                        end
                     else
                        begin
                        state <= STATE_PRE_IDLE;
                        end
                     end
                  end
               STATE_PRE_WAIT,	// unused state (guarantees exit)
               STATE_PRE_IDLE :
                  begin
                  if (block_addr[5:3] != last_lsbs[2:0])
                     begin
                     state <= STATE_IDLE;
                     end
                  end
            endcase
            end
         FRAC_PIXEL:
            begin
            case (state)
               STATE_WAIT,	// unused state (guarantees exit)
               STATE_IDLE :
                  begin
                  horizontal_flag_4d <= horizontal_flag_3d;
                  if (!v_blank_flag &&
                      (horizontal_flag_3d && !horizontal_flag_4d))
                     begin
                     last_lsbs <= block_addr[6:3];
                     block_start <= 1;
                     block_count <= 0;
                     block_address <= block_addr;
                     block_length <= 16*8-1;
                     block_word <= 0;
                     state <= STATE_LINE_A;
                     end
                  else
                     begin
                     if (!v_blank_flag && !p_blank_flag && !a_blank_flag &&
                         (block_addr[6:3] == last_lsbs[3:0]))
                        begin
                        block_start <= 1;
                        block_count <= 0;
                        block_word <= 0;
                        state <= STATE_LINE_A;
                        end
                     end
                  end
               STATE_LINE_B,	// unused state (guarantees exit)
               STATE_LINE_U,	// unused state (guarantees exit)
               STATE_LINE_D,	// unused state (guarantees exit)
               STATE_LINE_A :
                  begin
                  block_delta <= 128;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_start <= 0;
                     block_address <= pre_block_address;
                     block_word <= 0;
                     if (p_blank_flag)
                        begin
                        state <= STATE_IDLE;
                        end
                     else
                        begin
                        state <= STATE_PRE_IDLE;
                        end
                     end
                  end
               STATE_PRE_WAIT,	// unused state (guarantees exit)
               STATE_PRE_IDLE :
                  begin
                  if (block_addr[6:3] != last_lsbs[3:0])
                     begin
                     state <= STATE_IDLE;
                     end
                  end
            endcase
            end
         INT_ALWAYS:
            begin
            case (state)
               STATE_WAIT,	// unused state (guarantees exit)
               STATE_IDLE :
                  begin
                  horizontal_flag_4d <= horizontal_flag_3d;
                  if (!v_blank_flag &&
                      (horizontal_flag_3d && !horizontal_flag_4d))
                     begin
                     last_lsbs <= block_addr[6:3];
                     block_start <= 1;
                     block_count <= 2;
                     block_address <= block_addr;
                     block_length <= 4*8-1;
                     block_word <= 0;
                     state <= STATE_LINE_A;
                     end
                  else
                     begin
                     if (!v_blank_flag && !p_blank_flag && !a_blank_flag &&
                         (block_addr[4:3] == last_lsbs[1:0]))
                        begin
                        block_start <= 1;
                        block_count <= 2;
                        block_word <= 0;
                        state <= STATE_LINE_A;
                        end
                     end
                  end
               STATE_LINE_A :
                  begin
                  block_delta <= byte_width;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_address <= pre_block_address;
                     block_word <= 8;
                     state <= STATE_LINE_B;
                     end
                  end
               STATE_LINE_B :
                  begin
                  block_delta <= -{byte_width,1'b0};
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_address <= pre_block_address;
                     block_word <= 4;
                     state <= STATE_LINE_U;
                     end
                  end
               STATE_LINE_D,	// unused state (guarantees exit)
               STATE_LINE_U :
                  begin
                  block_delta <= byte_width + 32;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_start <= 0;
                     block_address <= pre_block_address;
                     block_word <= 0;
                     if (p_blank_flag)
                        begin
                        state <= STATE_IDLE;
                        end
                     else
                        begin
                        state <= STATE_PRE_IDLE;
                        end
                     end
                  end
               STATE_PRE_WAIT,	// unused state (guarantees exit)
               STATE_PRE_IDLE :
                  begin
                  if (block_addr[4:3] != last_lsbs[1:0])
                     begin
                     state <= STATE_IDLE;
                     end
                  end
            endcase
            end
         INT_BYNEED:
            begin
            case (state)
               STATE_IDLE :
                  begin
                  horizontal_flag_4d <= horizontal_flag_3d;
                  if (!v_blank_flag &&
                      (horizontal_flag_3d && !horizontal_flag_4d))
                     begin
                     last_lsbs <= block_addr[6:3];
                     block_start <= 1;
                     block_count <= 0;
                     block_address <= pre_block_addr;
                     block_length <= 6*8-1;
                     block_word <= 15;
                     state <= STATE_LINE_A;
                     end
                  else
                     begin
                     if (!v_blank_flag && !p_blank_flag && !a_blank_flag &&
                         (block_addr[4:3] == last_lsbs[1:0]))
                        begin
                        block_start <= 1;
                        block_count <= 0;
                        block_length <= 6*8-1;
                        block_word <= 15;
                        state <= STATE_LINE_A;
                        end
                     end
                  end
               STATE_LINE_A :
                  begin
                  block_delta <= byte_width + 8;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_start <= 0;
                     block_count <= 1;
                     block_address <= pre_block_address;
                     block_length <= 4*8-1;
                     block_word <= 8;
                     if (p_blank_flag)
                        begin
                        state <= STATE_WAIT;
                        end
                     else
                        begin
                        state <= STATE_PRE_WAIT;
                        end
                     end
                  end
               STATE_PRE_WAIT :
                  begin
                  if (block_addr[4:3] != last_lsbs[1:0])
                     begin
                     state <= STATE_WAIT;
                     end
                  end
               STATE_WAIT :
                  begin
                  block_delta <= -byte_width + 32 - 8;
                  if (block_partial_3d)
                     begin
                     block_start <= 1;
                     state <= STATE_LINE_B;
                     end
                  else
                     begin
                     horizontal_flag_4d <= horizontal_flag_3d;
                     if (!v_blank_flag &&
                         (horizontal_flag_3d && !horizontal_flag_4d))
                        begin
                        last_lsbs <= block_addr[6:3];
                        block_start <= 1;
                        block_count <= 0;
                        block_address <= pre_block_addr;
                        block_length <= 6*8-1;
                        block_word <= 15;
                        state <= STATE_LINE_A;
                        end
                     else
                        begin
                        if (!v_blank_flag && !p_blank_flag && !a_blank_flag &&
                            (block_addr[4:3] == last_lsbs[1:0]))
                           begin
                           block_start <= 1;
                           block_count <= 0;
                           block_address <= pre_block_address;
                           block_length <= 6*8-1;
                           block_word <= 15;
                           state <= STATE_LINE_A;
                           end
                        end
                     end
                  end
               STATE_LINE_B :
                  begin
                  block_delta <= -{byte_width,1'b0};
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_address <= pre_block_address;
                     block_word <= 4;
                     state <= STATE_LINE_U;
                     end
                  end
               STATE_LINE_D,	// unused state (guarantees exit)
               STATE_LINE_U :
                  begin
                  block_delta <= byte_width + 32 - 8;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_start <= 0;
                     block_address <= pre_block_address;
                     block_word <= 0;
                     if (p_blank_flag)
                        begin
                        state <= STATE_IDLE;
                        end
                     else
                        begin
                        state <= STATE_PRE_IDLE;
                        end
                     end
                  end
               STATE_PRE_IDLE :
                  begin
                  if (block_addr[4:3] != last_lsbs[1:0])
                     begin
                     state <= STATE_IDLE;
                     end
                  end
            endcase
            end
         INT_NEVER:
            begin
            case (state)
               STATE_WAIT,	// unused state (guarantees exit)
               STATE_IDLE :
                  begin
                  horizontal_flag_4d <= horizontal_flag_3d;
                  if (!v_blank_flag &&
                      (horizontal_flag_3d && !horizontal_flag_4d))
                     begin
                     last_lsbs <= block_addr[6:3];
                     block_start <= 1;
                     block_count <= 0;
                     block_address <= block_addr;
                     block_length <= 8*8-1;
                     block_word <= 0;
                     state <= STATE_LINE_A;
                     end
                  else
                     begin
                     if (!v_blank_flag && !p_blank_flag && !a_blank_flag &&
                         (block_addr[5:3] == last_lsbs[2:0]))
                        begin
                        block_start <= 1;
                        block_count <= 0;
                        block_word <= 0;
                        state <= STATE_LINE_A;
                        end
                     end
                  end
               STATE_LINE_B,	// unused state (guarantees exit)
               STATE_LINE_U,	// unused state (guarantees exit)
               STATE_LINE_D,	// unused state (guarantees exit)
               STATE_LINE_A :
                  begin
                  block_delta <= 64;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_start <= 0;
                     block_address <= pre_block_address;
                     block_word <= 0;
                     if (p_blank_flag)
                        begin
                        state <= STATE_IDLE;
                        end
                     else
                        begin
                        state <= STATE_PRE_IDLE;
                        end
                     end
                  end
               STATE_PRE_WAIT,	// unused state (guarantees exit)
               STATE_PRE_IDLE :
                  begin
                  if (block_addr[5:3] != last_lsbs[2:0])
                     begin
                     state <= STATE_IDLE;
                     end
                  end
            endcase
            end
         INT_PIXEL:
            begin
            case (state)
               STATE_WAIT,	// unused state (guarantees exit)
               STATE_IDLE :
                  begin
                  horizontal_flag_4d <= horizontal_flag_3d;
                  if (!v_blank_flag &&
                      (horizontal_flag_3d && !horizontal_flag_4d))
                     begin
                     last_lsbs <= block_addr[6:3];
                     block_start <= 1;
                     block_count <= 0;
                     block_address <= block_addr;
                     block_length <= 16*8-1;
                     block_word <= 0;
                     state <= STATE_LINE_A;
                     end
                  else
                     begin
                     if (!v_blank_flag && !p_blank_flag && !a_blank_flag &&
                         (block_addr[6:3] == last_lsbs[3:0]))
                        begin
                        block_start <= 1;
                        block_count <= 0;
                        block_word <= 0;
                        state <= STATE_LINE_A;
                        end
                     end
                  end
               STATE_LINE_B,	// unused state (guarantees exit)
               STATE_LINE_U,	// unused state (guarantees exit)
               STATE_LINE_D,	// unused state (guarantees exit)
               STATE_LINE_A :
                  begin
                  block_delta <= 128;
                  if (block_grant_3d && !block_grant_4d)
                     begin
                     block_start <= 0;
                     block_address <= pre_block_address;
                     block_word <= 0;
                     if (p_blank_flag)
                        begin
                        state <= STATE_IDLE;
                        end
                     else
                        begin
                        state <= STATE_PRE_IDLE;
                        end
                     end
                  end
               STATE_PRE_WAIT,	// unused state (guarantees exit)
               STATE_PRE_IDLE :
                  begin
                  if (block_addr[6:3] != last_lsbs[3:0])
                     begin
                     state <= STATE_IDLE;
                     end
                  end
            endcase
            end
      endcase
      end
   end

endmodule // vi_sync