// $Id: reality.v,v 1.1.1.1 2002/05/17 06:15:00 blythe Exp $
`timescale 1ns/1ns

module reality;

`include "reality.vh"
`include "define.vh"

wire clock;
wire reset_l;
wire test;

// R4200B interface
wire p_valid;
wire e_valid;
wire e_ok;
wire int;
wire [SYS_AD_SIZE-1:0] sys_ad;
wire [SYS_CMD_SIZE-1:0] sys_cmd;

// Rambus interface
wire rx_clk;
wire tx_clk;
wire bus_enable;
wire bus_ctrl;
wire [RAMBUS_DATA_SIZE-1:0] bus_data;
wire s_0;
wire s_1;
wire s_2;
wire s_3;
wire v_ref;
wire c_ctl_pgm;

// AD 16 interface
wire ad16_aleh;
wire ad16_alel;
wire ad16_read;
wire ad16_write;
wire [AD16_DATA_SIZE-1:0] ad16_data;


wire mask_ad16rw; // masks ad16_rd ad16_write

// PIF interface
wire pif_rsp;
wire pif_cmd;
wire pif_clock;
wire nmi_l;


// ABUS interface
wire abus_data;
wire abus_word;
wire abus_clock;

// VBUS interface
wire [VBUS_DATA_SIZE-1:0] vbus_data;
wire vbus_sync;
wire vbus_clock;

supply0 gnd;
supply1 vcc;


assign v_ref = vcc;
assign c_ctl_pgm = vcc;
assign tx_clk = rx_clk;

rcp rcp_0(.mclock_pad(clock), .reset_l_pad(reset_l), .test_pad(test),
    .p_valid_pad(p_valid), .e_valid_pad(e_valid),
    .e_ok_pad(e_ok), .int_pad(int), .sys_ad_pad(sys_ad),
    .sys_cmd_pad(sys_cmd), .bus_clk(rx_clk),
    .v_ref(v_ref), .c_ctl_pgm(c_ctl_pgm),
    .bus_enable_rac(bus_enable),
    .bus_ctrl_rac(bus_ctrl), .bus_data_rac(bus_data),
    .ad16_aleh_pad(ad16_aleh), .ad16_alel_pad(ad16_alel),
    .ad16_read_pad(ad16_read), .ad16_write_pad(ad16_write),
    .ad16_data_pad(ad16_data), .pif_rsp_pad(pif_rsp),
    .pif_cmd_pad(pif_cmd), .pif_clock_pad(pif_clock),
    .abus_data_pad(abus_data), .abus_word_pad(abus_word),
    .abus_clock_pad(abus_clock), .vbus_data_pad(vbus_data),
    .vbus_sync_pad(vbus_sync), .vclk_pad(vbus_clock));


r4200b r4200b_0(clock, reset_l, p_valid, e_valid, e_ok, int, sys_ad, sys_cmd, nmi_l);

pif pif_0 (pif_clock, reset_l,  pif_cmd, pif_rsp , nmi_l);


// Audio test DAC
test_adac test_adac_0( reset_l, 32'b0, abus_data, abus_clock, abus_word);


// ROM #0: address 0x08000000 (8 MB)
`ifdef ROM_0_PRESENT
mrom64m     #('b0100) rom_0(ad16_data, ad16_aleh, ad16_alel, gnd, ad16_read|mask_ad16rw);
`endif

// ROM #1: address 0x10000000 (8 MB)
`ifdef ROM_1_PRESENT
NI_MROM_64M #('b1000) rom_1(ad16_data, ad16_aleh, ad16_alel, gnd, ad16_read|mask_ad16rw);
`endif

// ROM #2: address 0x09000000 (8 MB)
`ifdef ROM_2_PRESENT
rwrom   #('b0110) rom_2(ad16_data, ad16_aleh, ad16_alel, ad16_write, ad16_read|mask_ad16rw);
`endif

`ifdef RDRAM_0_PRESENT
rdram rdram_0(rx_clk, tx_clk, bus_enable, bus_ctrl, bus_data, s_2, s_3, v_ref);
`endif

`ifdef RDRAM_1_PRESENT
rdram rdram_1(rx_clk, tx_clk, bus_enable, bus_ctrl, bus_data, vcc, s_0, v_ref);
`else
assign s_0 = vcc;
`endif

`ifdef RDRAM_1MBYTE_PRESENT
   rdram_8mb rdram_2(rx_clk, tx_clk, bus_enable, bus_ctrl, bus_data, s_0, s_1, v_ref);
   rdram_8mb rdram_3(rx_clk, tx_clk, bus_enable, bus_ctrl, bus_data, s_1, s_2, v_ref);
`else
   `ifdef RDRAM_23_PRESENT
      rdram rdram_2(rx_clk, tx_clk, bus_enable, bus_ctrl, bus_data, s_0, s_1, v_ref);
      rdram rdram_3(rx_clk, tx_clk, bus_enable, bus_ctrl, bus_data, s_1, s_2, v_ref);
   `else
      assign s_2 = s_0;
   `endif
`endif

cg cg_0(clock, reset_l, rx_clk, vbus_clock);
sync sync_0(rx_clk, reset_l, test, ad16_data, ad16_read, ad16_write, mask_ad16rw);


// Rambus pull up resistors
pullup (bus_data[0]);
pullup (bus_data[1]);
pullup (bus_data[2]);
pullup (bus_data[3]);
pullup (bus_data[4]);
pullup (bus_data[5]);
pullup (bus_data[6]);
pullup (bus_data[7]);
pullup (bus_data[8]);
pullup (bus_ctrl);
pullup (bus_enable);

// test and monitor modules
`ifdef GATE_LEVEL
`else
cbus_mon cbus_mon_0(clock, reset_l);
xbus_mon xbus_mon_0(clock, reset_l);
 `endif
reality_mon reality_mon_0(clock, reset_l);
mbus_mon mbus_mon_0(clock, reset_l, p_valid, e_valid, e_ok, int, sys_ad,sys_cmd);
`ifdef GATE_LEVEL
`ifdef RSP_MON
rsp_mon_gate rsp_mon_0(clock, reset_l);
`endif
`else
pbus_mon pbus_mon_0(ad16_aleh, ad16_alel, ad16_read, ad16_write, ad16_data);
`ifdef RSP_MON
rsp_mon rsp_mon_0(clock, reset_l);
`endif
// channel_monitor channel_monitor_0(vcc, s_0, rx_clk, bus_enable, bus_ctrl,
//    bus_data, 0);

`ifdef MSPAN_MON
mspan_mon mspan_mon_0(clock);
spandata_mon spandata_mon_0(clock, reset_l);
`endif

`endif

`ifdef MMAP_RDRAM
reg [1:256*8] filename;
initial if ($getstr$plusarg("mmap_rdram=", filename) == 1) begin 

`ifdef RDRAM_1_PRESENT
`ifdef RDRAM_23_PRESENT
    if ($rdram_mmap_init(filename, 4) == -1)
`else
    if ($rdram_mmap_init(filename, 2) == -1)
`endif
`else
    if ($rdram_mmap_init(filename, 1) == -1)
`endif
    begin
	$display("RDRAM mmap files never initialized");
	$finish;
    end
    
end

`endif // MMAP_RDRAM

// tab file modules

`ifdef PI_TAB
  pi_tab pi_tab_0();
`endif // PI_TAB

`ifdef ARB_TAB
  arb_tab arb_tab_0();
`endif // ARB_TAB

`ifdef AI_TAB
  ai_tab ai_tab_0();
`endif // AI_TAB

`ifdef MS_TAB
  ms_tab ms_tab_0();
`endif // MS_TAB

`ifdef RCP_TAB
  rcp_tab rcp_tab_0();
`endif // RCP_TAB

`ifdef VI_TAB
  vi_tab vi_tab_0();
`endif // VI_TAB

`ifdef MI_TAB
  mi_tab mi_tab_0();
`endif // MI_TAB

`ifdef SI_TAB
  si_tab si_tab_0();
`endif // SI_TAB

`ifdef TST_TAB
  tst_tab tst_tab_0();
`endif // TST_TAB

// extract tssi vectors for test (and fault grading)
`ifdef GATE_LEVEL
`else
rcp_test_tssi rcp_test_tssi_0();
rcp_full_tssi rcp_full_tssi_0();
rcp_attest_tab rcp_attest_tab();
rcp_hp330_tssi rcp_hp330_tssi_0();
`endif


endmodule