//****************************************************************************
//
// File: ai.tst 
//	 Test file for Audio Interface (AI)
//
// File Format:
//
// t <id> <arg1> <arg2> <arg3> <arg4>	- Run test id with the 4 args
//						where id   = decimal number
//						      argX = hex number
// q					- Quit testing and shutdown verilog 
//					  server
// 
//****************************************************************************

//****************************************************************************
// Configure RDRAM 
//
t 0000 00000000 00000000 00000000 00000000

//****************************************************************************
// Init RDRAM with pattern data (rdram_addr, nbytes, pattern_key)
t 0013 00000000 00000020 87654321 00000000

// Init Video Interface (VI) to get proper video clock signal into AI
t 0102 04400000 00000000 00000000 00000000

// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000

//****************************************************************************
// Test AI DMA: dram_address, nbytes

//****************************************************************************
// DMA 20 Bytes (RDRAM -> AI)					-> SHOULD PASS
//	Note: Address and data must be 8-byte aligned
//
t 0043 00000000 00000014 00000000 00000000
// Check for interrupt bit set (bit 2)
t 0104 04300008 00000004 00000000 00000000
// Clear interrupt bit
t 0102 0450000C 00000000 00000000 00000000

//****************************************************************************
// Here, we stall in verilog for X cycles to make sure that data is shifted 
// out to Audio DAC 
// Wait for around 3000 cycles
t 0014 00000300 00000000 00000000 00000000

//****************************************************************************
// QUIT
//****************************************************************************
q