ai_vector.tst 16.7 KB
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//****************************************************************************
//
// File: ai_vector.tst
//	 Vector Test file for Audio Interface (AI)
//
// File Format:
//
// t <id> <arg1> <arg2> <arg3> <arg4>	- Run test id with the 4 args
//						where id   = decimal number
//						      argX = hex number
// q					- Quit testing and shutdown verilog
//					  server
//
// modified by rhn 95Oct12 6pm
// for better fault coverage
//   added test for bit 23 of dma address
//   corrected data patterns in first 40 bytes
// note: delay of 101 between 16 byte DMA's needs to be tuned
//
//****************************************************************************

//****************************************************************************
// Audio Vector Tests
// Note, the audio output section runs off of Video Clock.
// These test may need to be bundled with the video tests
// which run at the vclk frequency not clock freq.

//****************************************************************************
// Test Audio Clock Generation divisors on Video Clock
//****************************************************************************
// Load and Decrement the dac_cntr observe the decremented count
// value in the audio status reg by pulling it accross sysad

// Force soft reset to audio section (set bit_rate = 0)
t 102 04500014 00000000 00000000 00000000

// load dac_rate reg with max dac count value
t 102 04500010 00003ffe 00000000 00000000

// set bit rate to 1 to kick off the load and decrement
t 102 04500014 00000001 00000000 00000000

// poll dac_cntr value from status reg till it reaches expected value
// need <= compare since dac_cntr decrements faster than we can read
// spin on dac_cnt decrementing past specified value		-> SHOULD PASS
t 0044 00000000 00003ffc 00000000 00000000

//Repeat for new dac count load
// Force soft reset to audio section (set bit_rate = 0)
t 102 04500014 00000000 00000000 00000000

// load dac_rate reg to toggle the complete carry chain
t 102 04500010 00002000 00000000 00000000

// set bit rate to 1 to kick off the load and decrement
t 102 04500014 00000001 00000000 00000000

// poll dac_cntr value from status reg till it reaches expected value
// need <= compare since dac_cntr decrements faster than we can read
// spin on dac_cnt decrementing past specified value            -> SHOULD PASS
t 0044 00000000 00001ffe 00000000 00000000

// end dac counter tests

// Test Audio State counter, using DMA at fastest rates
// dma data patterns test the state decode and are observed
// on external abus_data pins

// Configure RDRAM
// NOTE when combining multiple tests, dont do this config rdram here!!
// Note do this at initialization
t 0000 00000000 00000000 00000000 00000000

// Force soft reset to audio section (set bit_rate = 0)
t 102 04500014 00000000 00000000 00000000

//****************************************************************************
// Note: We should pre-initialize rdram and just point to it here
// Init RDRAM with pattern data
// Note: Loading RDRAM at address 0
// Note: Loading RDRAM at address 10
// Note: Loading RDRAM at address 20
// 32 bytes total

t 0102 00000000 0000ffff 00000000 00000000
t 0102 00000004 ffff0000 00000000 00000000
t 0102 00000008 0001fffe 00000000 00000000
t 0102 0000000c 0002fffd 00000000 00000000

t 0102 00000010 0004fffb 00000000 00000000
t 0102 00000014 0008fff7 00000000 00000000
t 0102 00000018 0010ffef 00000000 00000000
t 0102 0000001c 0020ffdf 00000000 00000000

t 0102 00000020 aa5555aa 00000000 00000000
t 0102 00000024 a5a55a5a 00000000 00000000

// Note: Loading RDRAM at address 40
// 16 bytes
t 0102 00000038 0040ffbf 00000000 00000000
t 0102 0000003c 0080ff7f 00000000 00000000
t 0102 00000040 0100feff 00000000 00000000
t 0102 00000044 0200fdff 00000000 00000000

// Note: Loading RDRAM at address 80
t 0102 00000078 0400fbff 00000000 00000000
t 0102 0000007c 0800f7ff 00000000 00000000
t 0102 00000080 1000efff 00000000 00000000
t 0102 00000084 2000dfff 00000000 00000000

// Note: Loading RDRAM at address 100, etc.
t 0102 000000f8 4000bfff 00000000 00000000
t 0102 000000fc 80007fff 00000000 00000000
t 0102 00000100 ffff0000 00000000 00000000
t 0102 00000104 fffe0001 00000000 00000000

t 0102 000001f8 fffd0002 00000000 00000000
t 0102 000001fc fffb0004 00000000 00000000
t 0102 00000200 fff70008 00000000 00000000
t 0102 00000204 ffef0010 00000000 00000000

t 0102 000003f8 ffdf0020 00000000 00000000
t 0102 000003fc ffbf0040 00000000 00000000
t 0102 00000400 ff7f0080 00000000 00000000
t 0102 00000404 feff0100 00000000 00000000

t 0102 000007f8 fdff0200 00000000 00000000
t 0102 000007fc fbff0400 00000000 00000000
t 0102 00000800 f7ff0800 00000000 00000000
t 0102 00000804 efff1000 00000000 00000000

t 0102 00000ff8 dfff2000 00000000 00000000
t 0102 00000ffc bfff4000 00000000 00000000
t 0102 00001000 7fff8000 00000000 00000000
t 0102 00001004 ffff0000 00000000 00000000

t 0102 00001ff8 11001ff8 00000000 00000000
t 0102 00001ffc 11001ffc 00000000 00000000
t 0102 00002000 22002000 00000000 00000000
t 0102 00002004 22002004 00000000 00000000

t 0102 00003ff8 30003ff8 00000000 00000000
t 0102 00003ffc 30003ffc 00000000 00000000
t 0102 00004000 44004000 00000000 00000000
t 0102 00004004 44004004 00000000 00000000

t 0102 00007ff8 50007ff8 00000000 00000000
t 0102 00007ffc 50007ffc 00000000 00000000
t 0102 00008000 60008000 00000000 00000000
t 0102 00008004 60008004 00000000 00000000

t 0102 0000fff8 7000fff8 00000000 00000000
t 0102 0000fffc 7000fffc 00000000 00000000
t 0102 00010000 88010000 00000000 00000000
t 0102 00010004 88010004 00000000 00000000

t 0102 0001fff8 9001fff8 00000000 00000000
t 0102 0001fffc 9001fffc 00000000 00000000
t 0102 00020000 a0020000 00000000 00000000
t 0102 00020004 a0020004 00000000 00000000

t 0102 0003fff8 b003fff8 00000000 00000000
t 0102 0003fffc b003fffc 00000000 00000000
t 0102 00040000 c0040000 00000000 00000000
t 0102 00040004 c0040004 00000000 00000000

t 0102 0007fff8 ffffffff 00000000 00000000
t 0102 0007fffc 00000000 00000000 00000000
t 0102 00080000 aaaaaaaa 00000000 00000000
t 0102 00080004 55555555 00000000 00000000

t 0102 000ffff8 ff0000ff 00000000 00000000
t 0102 000ffffc ff00ff00 00000000 00000000
t 0102 00100000 f0f00f0f 00000000 00000000
t 0102 00100004 f00f0ff0 00000000 00000000

t 0102 001ffff0 33cccc33 00000000 00000000
t 0102 001ffff4 3c3cc3c3 00000000 00000000
t 0102 001ffff8 cc3333cc 00000000 00000000
t 0102 001ffffc c3c33c3c 00000000 00000000

// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000085 00000001 00000000 00000000

// DMA 40 Bytes from address 0 (RDRAM -> AI)
//	Note: Address and data must be 8-byte aligned
//	Note: RDRAM address 0 being used, needs changed if retargeted
t 0043 00000000 00000028 00000000 00000000

// request a second dma to the double buffered dma engine
// DMA 16 Bytes around address 200000 (RDRAM -> AI)
t 0043 001ffff0 00000010 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000
t 0014 00000101 00000000 00000000 00000000

// DMA 16 Bytes around address 40 (RDRAM -> AI)
t 0043 00000038 00000010 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000

// DMA 16 Bytes around address 80 (RDRAM -> AI)
t 0043 00000078 00000010 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000

// DMA 16 Bytes around address 100 (RDRAM -> AI)
t 0043 000000f8 00000010 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000

// DMA 16 Bytes around address 200 (RDRAM -> AI)
t 0043 000001f8 00000010 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000

// DMA 16 Bytes around address 400 (RDRAM -> AI)
t 0043 000003f8 00000010 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000

// DMA 16 Bytes around address 800 (RDRAM -> AI)
t 0043 000007f8 00000010 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000

// DMA 16 Bytes around address 1000 (RDRAM -> AI)
t 0043 00000ff8 00000010 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000

// DMA 16 Bytes around address 2000 (RDRAM -> AI)
t 0043 00001ff8 00000010 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000

// DMA 16 Bytes around address 4000 (RDRAM -> AI)
t 0043 00003ff8 00000010 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000

// DMA 16 Bytes around address 8000 (RDRAM -> AI)
t 0043 00007ff8 00000010 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000

// DMA 16 Bytes around address 10000 (RDRAM -> AI)
t 0043 0000fff8 00000010 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000

// DMA 16 Bytes around address 20000 (RDRAM -> AI)
t 0043 0001fff8 00000010 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000

// DMA 16 Bytes around address 40000 (RDRAM -> AI)
t 0043 0003fff8 00000010 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000

// DMA 16 Bytes around address 80000 (RDRAM -> AI)
t 0043 0007fff8 00000010 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000

// DMA 16 Bytes around address 100000 (RDRAM -> AI)
t 0043 000ffff8 00000010 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000

// when interrupt bit is set, the first dma request has expired
// Poll /wait for audio interrupt bit set (bit 2)
//t 0104 04300008 00000004 00000000 00000000

//****************************************************************************
// Here, we stall in verilog for X cycles to make sure that data is shifted
// out to Audio DAC
// Wait for around 3000 cycles
// Need to optimize for test vector time
// DONT use TEST 14, It causes lots of Sysad activity
t 0014 00000300 00000000 00000000 00000000

// end state control and abus/abus_clk and abus_wrdsel test

// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000

//****************************************************************************
// Test AI length counter: repeatdly start a dma with a length and
// check for the count to decrement to next bit position
// relies on rdram data being previously loaded

// Note, maybe change dac rate counter to a smaller value
//****************************************************************************
// ** test msb bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
// Configure very slow clock rate to check bit rate counter
t 003 000003aa 00000007 00000000 00000000
// start ai dma  of specified length
t 0048 00000000 00020008 00000000 00000000
// stack up ai dma  of specified length
t 0048 00000000 0001fff0 00000000 00000000
// spin on length decrementing to specified value		-> SHOULD PASS
t 0049 00000000 0001fff8 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000

//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma  of specified length
t 0048 00000000 00010000 00000000 00000000
// spin on length decrementing to specified value               -> SHOULD PASS
t 0049 00000000 0000fff8 00000000 00000000
// stall
t 0014 00000101 00000000 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000

//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma  of specified length
t 0048 00000000 00008000 00000000 00000000
// spin on length decrementing to specified value               -> SHOULD PASS
t 0049 00000000 00007ff8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000

//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma  of specified length
t 0048 00000000 00004000 00000000 00000000
// spin on length decrementing to specified value               -> SHOULD PASS
t 0049 00000000 00003ff8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000

//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma  of specified length
t 0048 00000000 00002000 00000000 00000000
// spin on length decrementing to specified value               -> SHOULD PASS
t 0049 00000000 00001ff8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000

//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma  of specified length
t 0048 00000000 00001000 00000000 00000000
// spin on length decrementing to specified value               -> SHOULD PASS
t 0049 00000000 00000ff8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000

//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma  of specified length
t 0048 00000000 00000800 00000000 00000000
// spin on length decrementing to specified value               -> SHOULD PASS
t 0049 00000000 000007f8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000

//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma  of specified length
t 0048 00000000 00000400 00000000 00000000
// spin on length decrementing to specified value               -> SHOULD PASS
t 0049 00000000 000003f8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000

//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma  of specified length
t 0048 00000000 00000200 00000000 00000000
// spin on length decrementing to specified value               -> SHOULD PASS
t 0049 00000000 000001f8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000

//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma  of specified length
t 0048 00000000 00000100 00000000 00000000
// spin on length decrementing to specified value               -> SHOULD PASS
t 0049 00000000 000000f8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000

//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma  of specified length
t 0048 00000000 00000080 00000000 00000000
// spin on length decrementing to specified value               -> SHOULD PASS
t 0049 00000000 00000078 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000

//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma  of specified length
t 0048 00000000 00000040 00000000 00000000
// spin on length decrementing to specified value               -> SHOULD PASS
t 0049 00000000 00000038 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000

//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma  of specified length
t 0048 00000000 00000020 00000000 00000000
// spin on length decrementing to specified value               -> SHOULD PASS
t 0049 00000000 00000018 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000

//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma  of specified length
t 0048 00000000 00000010 00000000 00000000
// spin on length decrementing to specified value               -> SHOULD PASS
t 0049 00000000 00000008 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000

//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma  of specified length
t 0048 00000000 00000008 00000000 00000000
// spin on length decrementing to specified value               -> SHOULD PASS
t 0049 00000000 00000000 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000

//**  note will need to restore dac counter for any further tests

//****************************************************************************
// QUIT
//****************************************************************************
q