pi_v.tst
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//****************************************************************************
//
// File: pi.tst
// Manufacturing Vector Generation Tests for Peripheral Interface (PI)
//
// $Revision: 1.1.1.1 $
//
// File Format:
//
// t <id> <arg1> <arg2> <arg3> <arg4> - Run test id with the 4 args
// where id = decimal number
// argX = hex number
// q - Quit testing and shutdown verilog
// server
//
// This suite of tests require a preloaded ROM with the following data:
//
// ADDRESS DATA
// ------------- -----------------
// 0x000 - 0x0ff Sequential, 00-FF
// 0x100 - 0x17f 0xFF
// 0x180 - 0x1ff 0x00
// 0x200 - 0x27f 0x55
// 0x280 - 0x2ff 0xAA
//
//****************************************************************************
//****************************************************************************
// Configure RDRAM
t 0000 00000000 00000000 00000000 00000000
// Config PI Domain 1: lat, pwd, pgs, rls
t 0001 00000080 00000020 00000006 00000003
// Config PI Domain 2: lat, pwd, pgs, rls
t 0002 00000080 00000020 00000006 00000003
// Init RDRAM with pattern data (rdram_addr, nwords, pattern_key)
t 0013 00000000 00000080 81234567 00000000
//****************************************************************************
// W/R PI DRAM Address Reg: address, data, expected_data -> SHOULD PASS
t 0103 04600000 ffffffff 00fffffe 00000000
t 0103 04600000 00000000 00000000 00000000
t 0103 04600000 55555555 00555554 00000000
t 0103 04600000 aaaaaaaa 00aaaaaa 00000000
//****************************************************************************
// W/R PI Cartridge Address Reg: address, data, expected_data -> SHOULD PASS
t 0103 04600004 ffffffff fffffffe 00000000
t 0103 04600004 00000000 00000000 00000000
t 0103 04600004 55555555 55555554 00000000
t 0103 04600004 aaaaaaaa aaaaaaaa 00000000
//****************************************************************************
// Read from PI ROM address: address, data -> SHOULD PASS
t 0101 08000000 01000302 00000000 00000000
t 0101 08000004 05040706 00000000 00000000
t 0101 08000008 09080b0a 00000000 00000000
t 0101 0800000c 0d0c0f0e 00000000 00000000
//****************************************************************************
// W/R PI Cartridge: address, data, expected_data -> SHOULD PASS
t 0103 09000000 ffffffff ffffffff 00000000
t 0103 09000004 00000000 00000000 00000000
t 0103 097cfff8 55555555 55555555 00000000
t 0103 097cfffc aaaaaaaa aaaaaaaa 00000000
//****************************************************************************
// Test PI DMA: direction (1=from_RAM, 2=to_RAM),
// pi_address, ram_address, size
//****************************************************************************
// DMA 1: Length: 256B; Data: sequential -> SHOULD PASS
t 0023 00000002 08000000 00000000 00000100
// Now, test for DMA busy bits
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 08000000 00000000 00000100 00000000
//****************************************************************************
// DMA 2: Length: 128B; Data: 0xFFFF -> SHOULD PASS
t 0023 00000002 08000000 00000100 00000080
// Now, test for DMA busy bits
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 08000000 00000100 00000080 00000000
//****************************************************************************
// DMA 3: Length: 128B; Data: 0x0000 -> SHOULD PASS
t 0023 00000002 08000000 00000180 00000080
// Now, test for DMA busy bits
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 08000000 00000180 00000080 00000000
//****************************************************************************
// DMA 4: Length: 128B; Data: 0x5555 -> SHOULD PASS
t 0023 00000002 08000000 00000200 00000080
// Now, test for DMA busy bits
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 08000000 00000200 00000080 00000000
//****************************************************************************
// DMA 5: Length: 128B; Data: 0xAAAA -> SHOULD PASS
t 0023 00000002 08000000 00000280 00000080
// Now, test for DMA busy bits
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 08000000 00000280 00000080 00000000
//****************************************************************************
// DMA: Buffer-size length (128 bytes) xfer -> SHOULD PASS
t 0023 00000002 08000000 00000080 00000080
// Do IO read -> this should cause error bit to set
// ***** ERROR READ FAILED *******
t 0101 10000020 00100011 00000000 00000001
// Now, test for DMA busy
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
t 0105 08000000 00000080 00000080 00000000
//****************************************************************************
// Reset PI controller to turn off error bit
// First, read status to verify that error bit is set;
// then write to status register (bit 0) to reset PI controller
// and check for error bit to be cleared
t 0104 04600010 00000004 00000000 00000000
t 0102 04600010 00000001 00000000 00000000
t 0104 04600010 00000004 00000001 00000000
//****************************************************************************
// DMA long from DRAM -> ROM
// DMA: RDRAM -> ROM: across ROM boundary -> SHOULD PASS
// Rom size = 8MB = 0x7d0000
t 0023 00000001 097FFFF4 00000000 00000008
// Now, test for DMA busy bit
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
t 0105 097FFFF4 00000000 00000008 00000000
//****************************************************************************
// QUIT
//****************************************************************************
q