cp $ROOT/PR/rspsim/bpregre/ready/bpmult.s .
cp $ROOT/PR/rspsim/bpregre/ready/bptest0.s .
cp $ROOT/PR/rspsim/bpregre/ready/bptest1.s .
cp $ROOT/PR/rspsim/bpregre/ready/bptest2.s .
cp $ROOT/PR/rspsim/bpregre/ready/bptest3.s .
cp $ROOT/PR/rspsim/bpregre/ready/bptest4.s .
cp $ROOT/PR/rspsim/diregre/ready/di_ctlhz000.s .
cp $ROOT/PR/rspsim/diregre/ready/di_ctlhz001.s .
cp $ROOT/PR/rspsim/diregre/ready/di_ctlhz002.s .
cp $ROOT/PR/rspsim/diregre/ready/di_ctlhz010.s .
cp $ROOT/PR/rspsim/diregre/ready/di_ctlhz011.s .
cp $ROOT/PR/rspsim/diregre/ready/di_ctlhz012.s .
cp $ROOT/PR/rspsim/diregre/ready/di_ctlhz100.s .
cp $ROOT/PR/rspsim/diregre/ready/di_ctlhz101.s .
cp $ROOT/PR/rspsim/diregre/ready/di_ctlhz102.s .
cp $ROOT/PR/rspsim/diregre/ready/di_ctlhz110.s .
cp $ROOT/PR/rspsim/diregre/ready/di_ctlhz111.s .
cp $ROOT/PR/rspsim/diregre/ready/di_ctlhz112.s .
cp $ROOT/PR/rspsim/diregre/ready/di_ldst00.s .
cp $ROOT/PR/rspsim/diregre/ready/di_ldst01.s .
cp $ROOT/PR/rspsim/diregre/ready/di_ldst10.s .
cp $ROOT/PR/rspsim/diregre/ready/di_ldst20.s .
cp $ROOT/PR/rspsim/diregre/ready/di_reg.s .
cp $ROOT/PR/rspsim/diregre/ready/di_reghz0.s .
cp $ROOT/PR/rspsim/diregre/ready/di_reghz1.s .
cp $ROOT/PR/rspsim/diregre/ready/di_reghz2.s .
cp $ROOT/PR/rspsim/diregre/ready/di_reghz3.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest1.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest10.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest11.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest12.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest13.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest14.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest15.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest16.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest17.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest18.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest19.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest2.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest20.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest21.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest22.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest23.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest24.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest25.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest3.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest4.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest5.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest6.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest7.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest8.s .
cp $ROOT/PR/rspsim/ilregre/ready/iltest9.s .
cp $ROOT/PR/rspsim/suregre/ready/add1.s .
cp $ROOT/PR/rspsim/suregre/ready/addi1.s .
cp $ROOT/PR/rspsim/suregre/ready/addu2.s .
cp $ROOT/PR/rspsim/suregre/ready/and1.s .
cp $ROOT/PR/rspsim/suregre/ready/and2.s .
cp $ROOT/PR/rspsim/suregre/ready/beq1.s .
cp $ROOT/PR/rspsim/suregre/ready/bgez1.s .
cp $ROOT/PR/rspsim/suregre/ready/bgezal1.s .
cp $ROOT/PR/rspsim/suregre/ready/bgezal2.s .
cp $ROOT/PR/rspsim/suregre/ready/bgtz1.s .
cp $ROOT/PR/rspsim/suregre/ready/blez1.s .
cp $ROOT/PR/rspsim/suregre/ready/bltz1.s .
cp $ROOT/PR/rspsim/suregre/ready/bltzal1.s .
cp $ROOT/PR/rspsim/suregre/ready/bltzal2.s .
cp $ROOT/PR/rspsim/suregre/ready/bne1.s .
cp $ROOT/PR/rspsim/suregre/ready/cfc21.s .
cp $ROOT/PR/rspsim/suregre/ready/cfc22.s .
cp $ROOT/PR/rspsim/suregre/ready/ctc21.s .
cp $ROOT/PR/rspsim/suregre/ready/ctc22.s .
cp $ROOT/PR/rspsim/suregre/ready/init_regs.s .
cp $ROOT/PR/rspsim/suregre/ready/j1.s .
cp $ROOT/PR/rspsim/suregre/ready/jal1.s .
cp $ROOT/PR/rspsim/suregre/ready/jalr1.s .
cp $ROOT/PR/rspsim/suregre/ready/jr1.s .
cp $ROOT/PR/rspsim/suregre/ready/lb1.s .
cp $ROOT/PR/rspsim/suregre/ready/lbu1.s .
cp $ROOT/PR/rspsim/suregre/ready/lbv1.s .
cp $ROOT/PR/rspsim/suregre/ready/lbv2.s .
cp $ROOT/PR/rspsim/suregre/ready/lfv1.s .
cp $ROOT/PR/rspsim/suregre/ready/lh1.s .
cp $ROOT/PR/rspsim/suregre/ready/lhu1.s .
cp $ROOT/PR/rspsim/suregre/ready/lhv1.s .
cp $ROOT/PR/rspsim/suregre/ready/llv1.s .
cp $ROOT/PR/rspsim/suregre/ready/llv2.s .
cp $ROOT/PR/rspsim/suregre/ready/lpv1.s .
cp $ROOT/PR/rspsim/suregre/ready/lpv2.s .
cp $ROOT/PR/rspsim/suregre/ready/lqv1.s .
cp $ROOT/PR/rspsim/suregre/ready/lqv2.s .
cp $ROOT/PR/rspsim/suregre/ready/lrv1.s .
cp $ROOT/PR/rspsim/suregre/ready/lrv2.s .
cp $ROOT/PR/rspsim/suregre/ready/lsv1.s .
cp $ROOT/PR/rspsim/suregre/ready/lsv2.s .
cp $ROOT/PR/rspsim/suregre/ready/ltv1.s .
cp $ROOT/PR/rspsim/suregre/ready/lui1.s .
cp $ROOT/PR/rspsim/suregre/ready/luv1.s .
cp $ROOT/PR/rspsim/suregre/ready/luv2.s .
cp $ROOT/PR/rspsim/suregre/ready/lw1.s .
cp $ROOT/PR/rspsim/suregre/ready/mfc21.s .
cp $ROOT/PR/rspsim/suregre/ready/mfc22.s .
cp $ROOT/PR/rspsim/suregre/ready/mfc23.s .
cp $ROOT/PR/rspsim/suregre/ready/mfc24.s .
cp $ROOT/PR/rspsim/suregre/ready/mfc25.s .
cp $ROOT/PR/rspsim/suregre/ready/mfc26.s .
cp $ROOT/PR/rspsim/suregre/ready/mtc21.s .
cp $ROOT/PR/rspsim/suregre/ready/mtc22.s .
cp $ROOT/PR/rspsim/suregre/ready/mtc23.s .
cp $ROOT/PR/rspsim/suregre/ready/mtc24.s .
cp $ROOT/PR/rspsim/suregre/ready/mtc25.s .
cp $ROOT/PR/rspsim/suregre/ready/mtc26.s .
cp $ROOT/PR/rspsim/suregre/ready/nor1.s .
cp $ROOT/PR/rspsim/suregre/ready/nor2.s .
cp $ROOT/PR/rspsim/suregre/ready/or1.s .
cp $ROOT/PR/rspsim/suregre/ready/or2.s .
cp $ROOT/PR/rspsim/suregre/ready/sb1.s .
cp $ROOT/PR/rspsim/suregre/ready/sbv1.s .
cp $ROOT/PR/rspsim/suregre/ready/sbv2.s .
cp $ROOT/PR/rspsim/suregre/ready/sbv3.s .
cp $ROOT/PR/rspsim/suregre/ready/sbv4.s .
cp $ROOT/PR/rspsim/suregre/ready/sfv1.s .
cp $ROOT/PR/rspsim/suregre/ready/sfv2.s .
cp $ROOT/PR/rspsim/suregre/ready/sh1.s .
cp $ROOT/PR/rspsim/suregre/ready/shv1.s .
cp $ROOT/PR/rspsim/suregre/ready/shv2.s .
cp $ROOT/PR/rspsim/suregre/ready/sll1.s .
cp $ROOT/PR/rspsim/suregre/ready/sllv1.s .
cp $ROOT/PR/rspsim/suregre/ready/sllv2.s .
cp $ROOT/PR/rspsim/suregre/ready/slt1.s .
cp $ROOT/PR/rspsim/suregre/ready/slt2.s .
cp $ROOT/PR/rspsim/suregre/ready/sltu1.s .
cp $ROOT/PR/rspsim/suregre/ready/sltu2.s .
cp $ROOT/PR/rspsim/suregre/ready/slv1.s .
cp $ROOT/PR/rspsim/suregre/ready/slv2.s .
cp $ROOT/PR/rspsim/suregre/ready/slv3.s .
cp $ROOT/PR/rspsim/suregre/ready/slv4.s .
cp $ROOT/PR/rspsim/suregre/ready/spv1.s .
cp $ROOT/PR/rspsim/suregre/ready/spv2.s .
cp $ROOT/PR/rspsim/suregre/ready/spv3.s .
cp $ROOT/PR/rspsim/suregre/ready/spv4.s .
cp $ROOT/PR/rspsim/suregre/ready/sqv1.s .
cp $ROOT/PR/rspsim/suregre/ready/sqv2.s .
cp $ROOT/PR/rspsim/suregre/ready/sqv3.s .
cp $ROOT/PR/rspsim/suregre/ready/sqv4.s .
cp $ROOT/PR/rspsim/suregre/ready/sra1.s .
cp $ROOT/PR/rspsim/suregre/ready/srav1.s .
cp $ROOT/PR/rspsim/suregre/ready/srav2.s .
cp $ROOT/PR/rspsim/suregre/ready/srl1.s .
cp $ROOT/PR/rspsim/suregre/ready/srlv1.s .
cp $ROOT/PR/rspsim/suregre/ready/srlv2.s .
cp $ROOT/PR/rspsim/suregre/ready/srv1.s .
cp $ROOT/PR/rspsim/suregre/ready/srv2.s .
cp $ROOT/PR/rspsim/suregre/ready/srv3.s .
cp $ROOT/PR/rspsim/suregre/ready/srv4.s .
cp $ROOT/PR/rspsim/suregre/ready/ssv1.s .
cp $ROOT/PR/rspsim/suregre/ready/ssv2.s .
cp $ROOT/PR/rspsim/suregre/ready/ssv3.s .
cp $ROOT/PR/rspsim/suregre/ready/ssv4.s .
cp $ROOT/PR/rspsim/suregre/ready/stv1.s .
cp $ROOT/PR/rspsim/suregre/ready/sub1.s .
cp $ROOT/PR/rspsim/suregre/ready/subu2.s .
cp $ROOT/PR/rspsim/suregre/ready/suv1.s .
cp $ROOT/PR/rspsim/suregre/ready/suv2.s .
cp $ROOT/PR/rspsim/suregre/ready/suv3.s .
cp $ROOT/PR/rspsim/suregre/ready/suv4.s .
cp $ROOT/PR/rspsim/suregre/ready/sw1.s .
cp $ROOT/PR/rspsim/suregre/ready/swv1.s .
cp $ROOT/PR/rspsim/suregre/ready/xor1.s .
cp $ROOT/PR/rspsim/suregre/ready/xor2.s .
cp $ROOT/PR/rspsim/vuregre/src/dp_mul/dp_mul1.in .
cp $ROOT/PR/rspsim/vuregre/src/dp_recp/dp_recp_chain_mix.in .
cp $ROOT/PR/rspsim/vuregre/src/dp_recp/dp_recp_chain_neg.in .
cp $ROOT/PR/rspsim/vuregre/src/dp_recp/dp_recp_chain_pos.in .
cp $ROOT/PR/rspsim/vuregre/src/dp_recp/dp_recp_mix.in .
cp $ROOT/PR/rspsim/vuregre/src/dp_recp/dp_recp_neg.in .
cp $ROOT/PR/rspsim/vuregre/src/dp_recp/dp_recp_pos.in .
cp $ROOT/PR/rspsim/vuregre/src/dp_sqrt/dp_sqrt_chain_mix.in .
cp $ROOT/PR/rspsim/vuregre/src/dp_sqrt/dp_sqrt_chain_neg.in .
cp $ROOT/PR/rspsim/vuregre/src/dp_sqrt/dp_sqrt_chain_pos.in .
cp $ROOT/PR/rspsim/vuregre/src/dp_sqrt/dp_sqrt_mix.in .
cp $ROOT/PR/rspsim/vuregre/src/dp_sqrt/dp_sqrt_neg.in .
cp $ROOT/PR/rspsim/vuregre/src/dp_sqrt/dp_sqrt_pos.in .
cp $ROOT/PR/rspsim/vuregre/src/misc/test_intr.s .
cp $ROOT/PR/rspsim/vuregre/src/misc/test_pc.s .
cp $ROOT/PR/rspsim/vuregre/src/misc/test_sem_1.s .
cp $ROOT/PR/rspsim/vuregre/src/sp_recp/sp_recp_mix.in .
cp $ROOT/PR/rspsim/vuregre/src/sp_recp/sp_recp_neg.in .
cp $ROOT/PR/rspsim/vuregre/src/sp_recp/sp_recp_pos.in .
cp $ROOT/PR/rspsim/vuregre/src/sp_sqrt/sp_sqrt_mix.in .
cp $ROOT/PR/rspsim/vuregre/src/sp_sqrt/sp_sqrt_neg.in .
cp $ROOT/PR/rspsim/vuregre/src/sp_sqrt/sp_sqrt_pos.in .
cp $ROOT/PR/rspsim/vuregre/src/vabs/vabs_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vadd/vadd_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vaddc/vaddc_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vch/vch_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vcl/vcl_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vcr/vcr_v.in .
cp $ROOT/PR/rspsim/vuregre/src/veq/veq_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vge/vge_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vge_dbl/vge_dbl_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vlog/vand.in .
cp $ROOT/PR/rspsim/vuregre/src/vlog/vnand.in .
cp $ROOT/PR/rspsim/vuregre/src/vlog/vnor.in .
cp $ROOT/PR/rspsim/vuregre/src/vlog/vor.in .
cp $ROOT/PR/rspsim/vuregre/src/vlog/vxnor.in .
cp $ROOT/PR/rspsim/vuregre/src/vlog/vxor.in .
cp $ROOT/PR/rspsim/vuregre/src/vlt/vlt_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vlt_dbl/vlt_dbl_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmacf/vmacf_clamp.in .
cp $ROOT/PR/rspsim/vuregre/src/vmacf/vmacf_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmacq/vmacq_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmacq/vmacq_v1.in .
cp $ROOT/PR/rspsim/vuregre/src/vmacq/vmacq_v2.in .
cp $ROOT/PR/rspsim/vuregre/src/vmacu/vmacu_clamp.in .
cp $ROOT/PR/rspsim/vuregre/src/vmacu/vmacu_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmadh/vmadh_clamp.in .
cp $ROOT/PR/rspsim/vuregre/src/vmadh/vmadh_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmadh/vmadh_v1.in .
cp $ROOT/PR/rspsim/vuregre/src/vmadh1/vmadh1_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmadl/vmadl_clamp.in .
cp $ROOT/PR/rspsim/vuregre/src/vmadl/vmadl_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmadm/vmadm_clamp.in .
cp $ROOT/PR/rspsim/vuregre/src/vmadm/vmadm_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmadm/vmadm_v1.in .
cp $ROOT/PR/rspsim/vuregre/src/vmadn/vmadn_clamp.in .
cp $ROOT/PR/rspsim/vuregre/src/vmadn/vmadn_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmadn/vmadn_v1.in .
cp $ROOT/PR/rspsim/vuregre/src/vmov/vmov.in .
cp $ROOT/PR/rspsim/vuregre/src/vmrg/vmrg_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmudh/vmudh_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmudh/vmudh_v1.in .
cp $ROOT/PR/rspsim/vuregre/src/vmudh1/vmudh1_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmudl/vmudl_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmudl/vmudl_v1.in .
cp $ROOT/PR/rspsim/vuregre/src/vmudm/vmudm_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmudm/vmudm_v1.in .
cp $ROOT/PR/rspsim/vuregre/src/vmudn/vmudn_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmudn/vmudn_v1.in .
cp $ROOT/PR/rspsim/vuregre/src/vmulf/vmulf_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmulf/vmulf_v1.in .
cp $ROOT/PR/rspsim/vuregre/src/vmulq/vmulq_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmulu/vmulu_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vmulu/vmulu_v1.in .
cp $ROOT/PR/rspsim/vuregre/src/vne/vne_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vne_dbl/vne_dbl_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vrndn/vrndn_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vrndn/vrndn_v1.in .
cp $ROOT/PR/rspsim/vuregre/src/vrndp/vrndp_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vrndp/vrndp_v1.in .
cp $ROOT/PR/rspsim/vuregre/src/vsaw/vsaw.in .
cp $ROOT/PR/rspsim/vuregre/src/vsub/vsub_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vsubc/vsubc_h.in .
cp $ROOT/PR/rspsim/vuregre/src/vsubc/vsubc_q.in .
cp $ROOT/PR/rspsim/vuregre/src/vsubc/vsubc_v.in .
cp $ROOT/PR/rspsim/vuregre/src/vsubc/vsubc_w.in .