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issue.s 24.4 KB
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/****************************************************************
  This program improves toggle coverage for the instruction
  issue logic.
	
  Alignment of instructions to 64-bit boundaries, and misalignment
  with respect to 64-bit boundaries, is critical for testing
  issue logic.  Removal of nop's will cause changes in this
  alignment.
 ****************************************************************/

#include "suregre.h"

.base 0x04001000
        .data   0x04000000
        .word   0x00000000              /* Addr: 0x0000 */
        .word   0x00000000              /* Addr: 0x0004 */
        .word   0x00000000              /* Addr: 0x0008 */
        .word   0x00000000              /* Addr: 0x000C */
        .word   0x00000000              /* Addr: 0x0010 */
        .word   0x00000000              /* Addr: 0x0014 */
        .word   0x00000000              /* Addr: 0x0018 */
        .word   0x00000000              /* Addr: 0x001C */
        .word   0x00000000              /* Addr: 0x0020 */
        .word   0x00000000              /* Addr: 0x0024 */
        .word   0x00000000              /* Addr: 0x0028 */
        .word   0x00000000              /* Addr: 0x002C */
        .word   0x00000000              /* Addr: 0x0030 */
        .word   0x00000000              /* Addr: 0x0034 */
        .word   0x00000000              /* Addr: 0x0038 */
        .word   0x00000000              /* Addr: 0x003C */
        .word   0x00000000              /* Addr: 0x0040 */
        .word   0x00000000              /* Addr: 0x0044 */
        .word   0x00000000              /* Addr: 0x0048 */
        .word   0x00000000              /* Addr: 0x004C */
        .word   0x00000000              /* Addr: 0x0050 */
        .word   0x00000000              /* Addr: 0x0054 */
        .word   0x00000000              /* Addr: 0x0058 */
        .word   0x00000000              /* Addr: 0x005C */
        .word   0x00000000              /* Addr: 0x0060 */
        .word   0x00000000              /* Addr: 0x0064 */
        .word   0x00000000              /* Addr: 0x0068 */
        .word   0x00000000              /* Addr: 0x006C */
        .word   0x00000000              /* Addr: 0x0070 */
        .word   0x00000000              /* Addr: 0x0074 */
        .word   0x00000000              /* Addr: 0x0078 */
        .word   0x00000000              /* Addr: 0x007C */
        .word   0x9F9C6781              /* Addr: 0x0080 */
        .word   0x52C6B5FB              /* Addr: 0x0084 */
        .word   0x3EDE2F54              /* Addr: 0x0088 */
        .word   0xAF7F61DF              /* Addr: 0x008C */
        .word   0xC737CDE1              /* Addr: 0x0090 */
        .word   0x804872BF              /* Addr: 0x0094 */
        .word   0xF7A31956              /* Addr: 0x0098 */
        .word   0x03F72847              /* Addr: 0x009C */
        .word   0x59867287              /* Addr: 0x00A0 */
        .word   0x6AB59488              /* Addr: 0x00A4 */
        .word   0xD673CEEA              /* Addr: 0x00A8 */
        .word   0x44E56A7B              /* Addr: 0x00AC */
        .word   0x615D29A1              /* Addr: 0x00B0 */
        .word   0x4F1D8B54              /* Addr: 0x00B4 */
        .word   0x0BD55B37              /* Addr: 0x00B8 */
        .word   0x996AE45B              /* Addr: 0x00BC */
        .word   0x00010001              /* Addr: 0x00C0 */
        .word   0x00010001              /* Addr: 0x00C4 */
        .word   0x00010001              /* Addr: 0x00C8 */
        .word   0x00010001              /* Addr: 0x00CC */
        .word   0xffffffff              /* Addr: 0x00D0 */
        .word   0xffffffff              /* Addr: 0x00D4 */
        .word   0xffffffff              /* Addr: 0x00D8 */
        .word   0xffffffff              /* Addr: 0x00DC */
        .word   0x00030003              /* Addr: 0x00E0 */
        .word   0x00030003              /* Addr: 0x00E4 */
        .word   0x00030003              /* Addr: 0x00E8 */
        .word   0x00030003              /* Addr: 0x00EC */
        .word   0xBEE2018F              /* Addr: 0x00F0 */
        .word   0xD60B1305              /* Addr: 0x00F4 */
        .word   0x71690809              /* Addr: 0x00F8 */
        .word   0xD4DDCBCD              /* Addr: 0x00FC */

	.word   0x598629A1              /* Addr: 0x0100 */ 
	.word   0x0001ffff              /* Addr: 0x0104 */ 
	.word   0x0003000F              /* Addr: 0x0108 */  
	.word   0x00112847              /* Addr: 0x010C */ 
	.word   0x9F9CCDE1              /* Addr: 0x0110 */  
	.word   0x6AB58B54              /* Addr: 0x0114 */   
	.word   0x0001ffff              /* Addr: 0x0118 */   
	.word   0x000361DF              /* Addr: 0x011C */  
	.word   0x598629A1              /* Addr: 0x0120 */   
	.word   0x0001ffff              /* Addr: 0x0124 */   
	.word   0x0003000f
	.word   0x00112847              /* Addr: 0x012C */  


        LI(r0 , 0xFFFF, 0xFFFF);
        LI(r1 , 0x0101, 0x0101);
        LI(r2 , 0x0202, 0x0202);
        LI(r3 , 0x0303, 0x0303);
        LI(r4 , 0x0404, 0x0404);
        LI(r5 , 0x0505, 0x0505);
        LI(r6 , 0x0606, 0x0606);
        LI(r7 , 0x0707, 0x0707);
        LI(r8 , 0x0808, 0x0808);
        LI(r9 , 0x0909, 0x0909);
        LI(r10, 0x0A0A, 0x0A0A);
        LI(r11, 0x0B0B, 0x0B0B);
        LI(r12, 0x0C0C, 0x0C0C);
        LI(r13, 0x0D0D, 0x0D0D);
        LI(r14, 0x0E0E, 0x0E0E);
        LI(r15, 0x0F0F, 0x0F0F);
        LI(r16, 0x1010, 0x1010);
        LI(r17, 0x1111, 0x1111);
        LI(r18, 0x1212, 0x1212);
        LI(r19, 0x1313, 0x1313);
        LI(r20, 0x1414, 0x1414);
        LI(r21, 0x1515, 0x1515);
        LI(r22, 0x1616, 0x1616);
        LI(r23, 0x1717, 0x1717);
        LI(r24, 0x1818, 0x1818);
        LI(r25, 0x1919, 0x1919);
        LI(r26, 0x1A1A, 0x1A1A);
        LI(r27, 0x1B1B, 0x1B1B);
        LI(r28, 0x1C1C, 0x1C1C);
        LI(r29, 0x1D1D, 0x1D1D);
        LI(r30, 0x1E1E, 0x1E1E);
        LI(r31, 0x1F1F, 0x1F1F);

        lqv     v0[0], 0 (r0);
        vxor    v0 , v0, v0
        vxor    v1 , v0, v0
        vxor    v2 , v0, v0
        vxor    v3 , v0, v0
        vxor    v4 , v0, v0
        vxor    v5 , v0, v0
        vxor    v6 , v0, v0
        vxor    v7 , v0, v0
        vxor    v8 , v0, v0
        vxor    v9 , v0, v0
        vxor    v10, v0, v0
        vxor    v11, v0, v0
        vxor    v12, v0, v0
        vxor    v13, v0, v0
        vxor    v14, v0, v0
        vxor    v15, v0, v0
        vxor    v16, v0, v0
        vxor    v17, v0, v0
        vxor    v18, v0, v0
        vxor    v19, v0, v0
        vxor    v20, v0, v0
        vxor    v21, v0, v0
        vxor    v22, v0, v0
        vxor    v23, v0, v0
        vxor    v24, v0, v0
        vxor    v25, v0, v0
        vxor    v26, v0, v0
        vxor    v27, v0, v0
        vxor    v28, v0, v0
        vxor    v29, v0, v0
        vxor    v30, v0, v0
        vxor    v31, v0, v0

	ori	r31, r0, 0xff
	ori	r29, r0, 0x800
		
/* *** issue_kill_unit_f_s_haz_first_vu_us2 *** */
/* *** issue_kill_unit_f_s_haz_first_vu_us2a *** */
/* *** issue_kill_unit_f_s_haz_term_vu9 *** */
/* *** issue_kill_unit_f_s_haz_term_vu_c *** */
/* *** issue_kill_unit_s_f_haz_second_ctcf_vc2 *** */
/* check that vu use_vc2/ctc2_vc2 are not dual issued */

	addi	r1, r0, 0x0
	ctc2	r0, v0
	lqv	v5, 0xd0(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x70(r0)	
	ori 	r4, r0, 0x93
	ctc2	r4, v2
	ctc2	r0, v1
	ori 	r4, r0, 0xff
	ctc2	r4, v0
	ori	r27, r0, 0x93
	nop
	vnoop 				/* aligned */	/* s_f */
	vcl	v7, v5, v6
	ctc2	r0, v2
	nop
	nop
	nop
	nop
	cfc2	r30, v1
	bne	r30, r27, Fail
	sqv	v7, -16(r29)

	addi	r1, r0, 0x1
	ctc2	r0, v0
	lqv	v5, 0xd0(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x70(r0)	
	ori 	r4, r0, 0x93
	ctc2	r4, v2
	ctc2	r0, v1
	ori 	r4, r0, 0xff
	ctc2	r4, v0
	ori	r27, r0, 0x93
	nop
	vnoop				/* f_s */
	vcl	v7, v5, v6		/* aligned */
	ctc2	r0, v2
	nop
	nop
	nop
	nop
	cfc2	r30, v1
	bne	r30, r27, Fail
	sqv	v7, 0x0(r29)
	
/* *** issue_kill_unit_s_f_haz_term_su0 *** */
/* check that vu load/use_vs are not dual issued */
	
	addi	r1, r0, 0x2
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)
	nop
	nop				/* aligned */	/* s_f */
	lqv	v5, 0x80(r0)
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x10(r29)
	
	addi	r1, r0, 0x3
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)
	nop
	nop				/* f_s */
	lqv	v5, 0x80(r0)		/* aligned */
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x20(r29)
	
/* *** issue_kill_unit_s_f_haz_term_su1 *** */
/* check that vu load/use_vt are not dual issued */
	
	addi	r1, r0, 0x4
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)	
	nop				/* aligned */	/* s_f */
	lqv	v6, 0x80(r0)
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x30(r29)

	addi	r1, r0, 0x5
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)	
	nop				/* f_s */
	lqv	v6, 0x80(r0)		/* aligned */
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x40(r29)

/* *** issue_kill_unit_s_f_haz_term_su2 *** */
/* check that vu load/write_vd are not dual issued */
	
	addi	r1, r0, 0x6
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x80(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)	
	nop				/* aligned */	/* s_f */
	lqv	v7, 0x90(r0)
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x50(r29)

	addi	r1, r0, 0x7
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x80(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)	
	nop				/* f_s */
	lqv	v7, 0x90(r0)		/* aligned */
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x60(r29)

/* *** issue_kill_unit_f_s_haz_term_su3 *** */
/* check that vu mtc2/use_vs are not dual issued */

	addi	r1, r0, 0x8
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)	
	nop				/* aligned */	/* s_f */
	mtc2	r1, v5[2]
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	mfc2	r28, v7[2]
	bne	r28, r1, Fail
	sqv	v7, 0x70(r29)

	addi	r1, r0, 0x9
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)	
	nop
	nop				/* f_s */
	mtc2	r1, v5[2]		/* aligned */
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	mfc2	r28, v7[2]
	bne	r28, r1, Fail
	sqv	v7, 0x80(r29)

/* *** issue_kill_unit_f_s_haz_term_su4 *** */
/* *** issue_kill_unit_f_s_haz_term_su_b *** */
/* *** issue_kill_unit_sav_su_first_hazard *** */
/* check that vu mtc2/use_vt are not dual issued */
	
	addi	r1, r0, 0xa
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)
	nop
	nop				/* aligned */	/* s_f */
	mtc2	r1, v6[2]
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	mfc2	r28, v7[2]
	bne	r28, r1, Fail
	sqv	v7, 0x90(r29)

	addi	r1, r0, 0xb
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)
	nop
	nop				/* f_s */
	mtc2	r1, v6[2]		/* aligned */
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	mfc2	r28, v7[2]
	bne	r28, r1, Fail
	sqv	v7, 0xa0(r29)

/* *** issue_kill_unit_f_s_haz_term_su5 *** */
/* *** issue_kill_unit_f_s_haz_term_su_b *** */
/* *** issue_kill_unit_sav_su_first_hazard *** */
/* check that vu mtc2/write_vd are not dual issued */
	
	addi	r1, r0, 0xc
	ctc2	r0, v0
	lqv	v5, 0x80(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)
	nop
	nop				/* aligned */	/* s_f */
	mtc2	r1, v7[2]
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0xb0(r29)

	addi	r1, r0, 0xd
	ctc2	r0, v0
	lqv	v5, 0x80(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)	
	nop				/* f_s */
	mtc2	r1, v7[2]		/* aligned */
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0xc0(r29)

/* *** issue_kill_unit_f_s_haz_term_su6 *** */
/* *** issue_kill_unit_f_s_haz_term_su_b *** */
/* *** issue_kill_unit_sav_su_first_hazard *** */
/* *** issue_xpose_1_c *** */
/* check that vu ltv/use_vs+ are not dual issued */
	
	addi	r1, r0, 0xe
	ctc2	r0, v0
	sh	r1, 0x8a(r0)
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)
	nop
	nop				/* aligned */	/* s_f */
	ltv	v0[0], 0x80(r0)
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	mfc2	r28, v7[10]
	bne	r28, r1, Fail
	sqv	v7, 0xd0(r29)

	addi	r1, r0, 0xf
	ctc2	r0, v0
	sh	r1, 0x8a(r0)
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)	
	nop				/* f_s */
	ltv	v0[0], 0x80(r0)		/* aligned */
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	mfc2	r28, v7[10]
	bne	r28, r1, Fail
	sqv	v7, 0xe0(r29)

/* *** issue_kill_unit_f_s_haz_term_su7 *** */
/* *** issue_kill_unit_f_s_haz_term_su_b *** */
/* *** issue_kill_unit_sav_su_first_hazard *** */
/* check that vu ltv/use_vt+ are not dual issued */
	
	addi	r1, r0, 0x10
	ctc2	r0, v0
	sh	r1, 0x8c(r0)
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)	
	nop				/* aligned */	/* s_f */
	ltv	v0[0], 0x80(r0)
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	mfc2	r28, v7[12]
	bne	r28, r1, Fail
	sqv	v7, 0xf0(r29)

	addi	r1, r0, 0x11
	ctc2	r0, v0
	sh	r1, 0x8c(r0)
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)	
	nop				/* f_s */
	ltv	v0[0], 0x80(r0)		/* aligned */
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	mfc2	r28, v7[12]
	bne	r28, r1, Fail
	sqv	v7, 0x100(r29)

/* *** issue_kill_unit_f_s_haz_term_su8 *** */
/* *** issue_kill_unit_f_s_haz_term_su_c *** */
/* *** issue_kill_unit_sav_su_first_hazard *** */
/* check that vu ltv/write_vd+ are not dual issued */
	
	addi	r1, r0, 0x12
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)
	nop
	nop				/* aligned */	/* s_f */
	ltv	v0[0], 0x80(r0)
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	mfc2	r28, v7[14]
	bne	r28, r0, Fail
	sqv	v7, 0x110(r29)

	addi	r1, r0, 0x13
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)
	nop
	nop				/* f_s */
	ltv	v0[0], 0x80(r0)		/* aligned */
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	mfc2	r28, v7[14]
	bne	r28, r0, Fail
	sqv	v7, 0x120(r29)

/* *** issue_kill_unit_f_s_haz_term_su9 *** */
/* *** issue_kill_unit_f_s_haz_term_su_c *** */
/* *** issue_kill_unit_sav_su_first_hazard *** */
/* check that vu ctc2_vc0/use_vc0 are not dual issued */
	
	addi	r1, r0, 0x14
	ctc2	r0, v0
	addi	r2, r0, 0xff
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0xc0(r0)	
	nop				/* aligned */	/* s_f */
	ctc2	r2, v0
	vadd	v7, v5, v6
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x130(r29)

	addi	r1, r0, 0x15
	ctc2	r0, v0
	addi	r2, r0, 0xff
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0xc0(r0)
	nop	
	nop				/* f_s */
	ctc2	r2, v0			/* aligned */
	vadd	v7, v5, v6
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x140(r29)

/* *** issue_kill_unit_f_s_haz_term_su10 *** */
/* *** issue_kill_unit_f_s_haz_term_su_c *** */
/* *** issue_kill_unit_sav_su_first_hazard *** */
/* check that vu ctc2_vc1/use_vc1 are not dual issued */

	ori	r5, r0, 0x80
	addi	r1, r0, 0x16
	ctc2	r0, v0
	addi	r2, r0, 0xff
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x80(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x70(r0)	
	lsv	v8[2], 0x2(r5)	
	lsv	v8[4], 0x4(r5)	
	lsv	v8[8], 0x8(r5)
	nop
	nop				/* aligned */	/* s_f */
	ctc2	r1, v1
	vmrg	v7, v6, v5
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x150(r29)

	addi	r1, r0, 0x17
	ctc2	r0, v0
	addi	r2, r0, 0xff
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x80(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x70(r0)	
	lsv	v8[0], 0x0(r5)	
	lsv	v8[2], 0x2(r5)	
	lsv	v8[4], 0x4(r5)	
	lsv	v8[8], 0x8(r5)
	nop
	nop				/* f_s */
	ctc2	r1, v1			/* aligned */
	vmrg	v7, v6, v5
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x160(r29)

/* *** issue_kill_unit_f_s_haz_term_su11 *** */
/* *** issue_kill_unit_f_s_haz_term_su_c *** */
/* *** issue_kill_unit_sav_su_first_hazard *** */
/* *** issue_kill_unit_f_s_haz_first_ctc2_vc2 *** */
/* *** issue_kill_unit_f_s_haz_second_vu_us2 *** */
/* *** issue_kill_unit_f_s_haz_second_vu_us2a *** */
/* check that vu ctc2_vc2/use_vc2 are not dual issued */

	addi	r1, r0, 0x18
	ctc2	r0, v0
	lqv	v5, 0xd0(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x70(r0)	
	ctc2	r0, v1
	ori 	r4, r0, 0xff
	ctc2	r4, v0
	ori	r28, r0, 0x0093
	ori 	r4, r0, 0x93
	nop
	nop				/* aligned */	/* s_f */
	ctc2	r4, v2
	vcl	v7, v5, v6
	nop
	nop
	nop
	nop
	cfc2	r30, v1
	bne	r30, r28, Fail
	sqv	v7, 0x170(r29)

	addi	r1, r0, 0x19
	ctc2	r0, v0
	lqv	v5, 0xd0(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x70(r0)	
	ctc2	r0, v1
	ori 	r4, r0, 0xff
	ctc2	r4, v0
	ori	r28, r0, 0x0093
	ori 	r4, r0, 0x93
	nop				/* f_s */
	ctc2	r4, v2			/* aligned */
	vcl	v7, v5, v6
	nop
	nop
	nop
	nop
	cfc2	r30, v1
	bne	r30, r28, Fail
	sqv	v7, 0x180(r29)

/* *** issue_kill_unit_f_s_haz_term_vu2 *** */
/* check that vu dest/mfc2 dest are not dual issued */
	
	addi	r1, r0, 0x1a
	ctc2	r0, v0
	lqv	v5, 0x80(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lh	r28, 0x80(r0)
	nop
	vnoop				/* aligned */	/* s_f */
	vxor	v7, v5, v6
	mfc2	r30, v7[0]
	nop
	nop
	nop
	nop
	bne	r30, r28, Fail
	sqv	v7, 0x190(r29)

	addi	r1, r0, 0x1b
	ctc2	r0, v0
	lqv	v5, 0x80(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lh	r28, 0x80(r0)	
	vnoop				/* f_s */
	vxor	v7, v5, v6		/* aligned */
	mfc2	r30, v7[0]
	nop
	nop
	nop
	nop
	bne	r30, r28, Fail
	sqv	v7, 0x1a0(r29)

/* *** issue_kill_unit_f_s_haz_term_vu3 *** */
/* check that vu dest/mtc2 dest are not dual issued */
	
	addi	r1, r0, 0x1c
	ctc2	r0, v0
	lqv	v5, 0x80(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)
	mtc2	r1, v8[0]
	nop
	vnoop				/* aligned */	/* s_f */
	vxor	v7, v5, v6
	mtc2	r1, v7[0]
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x1b0(r29)

	addi	r1, r0, 0x1d
	ctc2	r0, v0
	lqv	v5, 0x80(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)
	mtc2	r1, v8[0]
	nop
	vnoop				/* f_s */
	vxor	v7, v5, v6		/* aligned */
	mtc2	r1, v7[0]
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x1c0(r29)

/* *** issue_kill_unit_f_s_haz_term_vu5 *** */
/* check that vu write/store are not dual issued */
	
	addi	r1, r0, 0x1e
	ctc2	r0, v0
	lqv	v5, 0x80(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lhu	r8, 0x8e(r0)	
	vnoop				/* aligned */	/* s_f */
	vxor	v7, v5, v6
	stv	v0[0], 0xf0(r0)
	nop
	nop
	nop
	nop
	lhu	r30, 0xfe(r0)	
	bne	r30, r8, Fail
	sqv	v7, 0x1d0(r29)

	addi	r1, r0, 0x1f
	ctc2	r0, v0
	lqv	v5, 0x80(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lhu	r8, 0x8e(r0)
	nop
	vnoop				/* f_s */
	vxor	v7, v5, v6		/* aligned */
	stv	v0[0], 0xf0(r0)
	nop
	nop
	nop
	nop
	lhu	r30, 0xfe(r0)	
	bne	r30, r8, Fail
	sqv	v7, 0x1e0(r29)

/* *** issue_kill_unit_f_s_haz_term_vu6 *** */
/* check that vu write/vu lwv are not dual issued */
	
	addi	r1, r0, 0x20
	ctc2	r0, v0
	lqv	v5, 0x80(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lhu	r8, 0x8e(r0)
	nop
	vnoop				/* aligned */	/* s_f */
	vxor	v7, v5, v6
	lwv	v0[0], 80(r0)
	nop
	nop
	nop
	nop
	mfc2	r30, v7[14]
	bne	r30, r8, Fail
	sqv	v7, 0x1f0(r29)

	addi	r1, r0, 0x21
	ctc2	r0, v0
	lqv	v5, 0x80(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lhu	r8, 0x8e(r0)
	nop
	vnoop				/* f_s */
	vxor	v7, v5, v6		/* aligned */
	lwv	v0[0], 80(r0)
	nop
	nop
	nop
	nop
	mfc2	r30, v7[14]
	bne	r30, r8, Fail
	sqv	v7, 0x200(r29)

/* *** issue_kill_unit_f_s_haz_term_vu7 *** */
/* check that vu use_vc0/ctc2_vc0 are not dual issued */
	
	addi	r1, r0, 0x22
	ori	r4, r0, 0xff
	ctc2	r4, v0
	lqv	v5, 0xc0(r0)	
	lqv	v6, 0xc0(r0)
	lqv	v7, 0x70(r0)	
	lqv	v8, 0xe0(r0)	
	vnoop				/* aligned */	/* s_f */
	vadd	v7, v5, v6
	ctc2	r0, v0
	ctc2	r0, v1
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x210(r29)

	addi	r1, r0, 0x23
	ori	r4, r0, 0xff
	ctc2	r4, v0
	lqv	v5, 0xc0(r0)	
	lqv	v6, 0xc0(r0)
	lqv	v7, 0x70(r0)	
	lqv	v8, 0xe0(r0)	
	vnoop				/* f_s */
	vadd	v7, v5, v6		/* aligned */
	ctc2	r0, v0
	ctc2	r0, v1
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x220(r29)

/* *** issue_kill_unit_f_s_haz_term_vu8 *** */
/* *** issue_kill_unit_f_s_haz_term_vu_c *** */
/* check that vu write_vc1/cfc2_vc1 are not dual issued */
/* this is done in the previous test */
/*	
	vnoop				aligned	s_f 
	veq	vd, vs, vt
	cfc2	rx, v1

	vnoop			 	f_s 
	veq	vd, vs, vt	 	aligned 
	cfc2	rx, v1
*/
	
/* *** issue_muxed_sav_xp *** */
/* *** issue_sav_xpose *** */
/* *** issue_st_xpose_fst *** */
/* *** issue_st_xpose_snd *** */
/* *** issue_rd_xpose_fst *** */
/* *** issue_rd_xpose_snd *** */
/* *** issue_xpose_1_a *** */
/* *** issue_xpose_1_b *** */
/* *** issue_xpose_1_d *** */
/* *** issue_xpose_2_a *** */
/* *** issue_xpose_2_b *** */
/* check the issue of transpose instructions */

	addi	r1, r0, 0x24
	lqv	v16, 0x80(r0)
	lqv	v17, 0x90(r0)
	lqv	v18, 0xa0(r0)
	lqv	v19, 0xb0(r0)
	lqv	v20, 0xc0(r0)
	lqv	v21, 0xd0(r0)
	lqv	v22, 0xe0(r0)
	lqv	v23, 0xf0(r0)

	lqv	v24, 0xa0(r0)
	lqv	v25, 0xb0(r0)
	lqv	v26, 0xc0(r0)
	lqv	v27, 0xd0(r0)
	lqv	v28, 0xe0(r0)
	lqv	v29, 0xf0(r0)
	lqv	v30, 0x80(r0)
	lqv	v31, 0x90(r0)
	
	nop
	nop
	and	r17, r15, r16		/* aligned */
	vxor	v14, v15, v16
	and	r27, r25, r26		/* aligned */
	vxor	v7, v5, v6
	vnoop				/* aligned */
	stv	v24[0], 0x230(r29)	/* rd_xpose_snd */
	nop				/* aligned */	/* muxed_sav_xp <- st_xpose_snd */
	stv	v16[0], 0x240(r29)	/* rd_xpose_snd */
	nop				/* muxed_sav_xp <- rd_xpose_snd */
	lqv	v7, 0x230(r29)
	lqv	v8, 0x100(r0)
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	nop

	addi	r1, r0, 0x25
	lqv	v7, 0x240(r29)
	lqv	v8, 0x110(r0)
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	nop

	addi	r1, r0, 0x26
	nop	
	and	r17, r15, r16		/* aligned */
	vxor	v14, v15, v16
	and	r27, r25, r26		/* aligned */
	vxor	v7, v5, v6
	stv	v24[0], 0x250(r29)	/* aligned */	/* rd_xpose_fst */
	nop
	lqv	v7, 0x250(r29)
	lqv	v8, 0x120(r0)
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	nop

/*	
   assign rd_xpose_snd = rd_inst[31] && (rd_inst[14:11]==4'b1011);
   assign rd_xpose_fst = rd_inst[63] && (rd_inst[46:43]==4'b1011);
   spasdffen_1_0 fst_xp_vu_ff (st_xpose_snd, st_xpose_snd_n, rd_xpose_snd, save_rd_inst, clk, reset_l);
   spasdffen_1_0 snd_xp_vu_ff (st_xpose_fst, st_xpose_fst_n, rd_xpose_fst, save_rd_inst, clk, reset_l);
   assign muxed_sav_xp =prev_stalled ? st_xpose_snd : rd_xpose_snd;
   spasdffen_1_0 su_sav_xp_ff (sav_xpose, sav_xpose_n, muxed_sav_xp,adv_ir, clk,reset_l);
   assign save_rd_inst = should_have_stalled && !prev_stalled;
   spasdff_1_0_h prev_imem_stall_ff (prev_stalled, prev_stalled_n, should_have_stalled, clk, reset_l);	
   nr02d3 nr_su_sel_enc_0 (.a1(fst_rd_vu_custom), .a2(odd_target_custom), .zn(su_inst_sel_enc[0]));

   nd02d2 nd_su_sel_enc_1a (.a1(loc_prev_stalled), .a2(fst_st_vu), .zn(su_sel_enc_1a));
   nd02d2 nd_su_sel_enc_1b (.a1(loc_prev_stalled), .a2(odd_target_custom), .zn(su_sel_enc_1b));
   nd03d2 nd_su_sel_enc_1 (.a1(su_sel_enc_1a), .a2(su_sel_enc_1b), .a3(sav_su_n), .zn(su_inst_sel_enc[1]));
   nd03d2 nd_su_sel_enc_3 (.a1(su_sel_enc_1a), .a2(su_sel_enc_1b), .a3(sav_su_n), .zn(su_inst_sel_enc[3]));
   nd03d2 nd_su_sel_enc_4 (.a1(su_sel_enc_1a), .a2(su_sel_enc_1b), .a3(sav_su_n), .zn(su_inst_sel_enc[4]));
   nd03d2 nd_su_sel_enc_5 (.a1(su_sel_enc_1a), .a2(su_sel_enc_1b), .a3(sav_su_n), .zn(su_inst_sel_enc[5]));
   mx21d1h mx_xpose_1_a (.i0(rd_xpose_snd), .i1(st_xpose_snd), .s(su_inst_sel_enc[1]), .z(xpose_1_a));
   mx21d1h mx_xpose_1_b (.i0(rd_xpose_fst), .i1(st_xpose_snd), .s(su_inst_sel_enc[3]), .z(xpose_1_b));
   mx21d1h mx_xpose_1_d (.i0(st_xpose_fst), .i1(sav_xpose), .s(su_inst_sel_enc[5]), .z(xpose_1_d));
   mx21d1h mx_xpose_2_a (.i0(xpose_1_a), .i1(xpose_1_c), .s(su_inst_sel_enc[2]), .z(xpose_2_a));
   mx21d1h mx_xpose_2_b (.i0(xpose_1_b), .i1(xpose_1_d), .s(su_inst_sel_enc[2]), .z(xpose_2_b));
*/

/* *** issue_old_br_addr[11,9:7,5,3] *** */

	jal 0xfec	
	nop


        ori     r1, r0, 0xFEED;
Fail:
        sw      r1, 0(r0)
        nop
        nop
        nop
        nop
        break
	nop
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	nop

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	jr	r31
	nop

	break			/* should never get here */
	nop
	nop