setintmask.s 2.33 KB
/**************************************************************************
 *									  *
 *		 Copyright (C) 1994, Silicon Graphics, Inc.		  *
 *									  *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright law.  They  may  not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *									  *
 **************************************************************************/

#include <asm.h>
#include <regdef.h>
#include <R4300.h>
#include <rcp.h>
#include <os.h>
#include "threadasm.h"

	.rdata
	/*
	 * RCP interrupt mask table
	 */
.globl __osRcpImTable
__osRcpImTable:
	.half 0x555, 0x556, 0x559, 0x55a, 0x565, 0x566, 0x569, 0x56a
	.half 0x595, 0x596, 0x599, 0x59a, 0x5a5, 0x5a6, 0x5a9, 0x5aa
	.half 0x655, 0x656, 0x659, 0x65a, 0x665, 0x666, 0x669, 0x66a
	.half 0x695, 0x696, 0x699, 0x69a, 0x6a5, 0x6a6, 0x6a9, 0x6aa
	.half 0x955, 0x956, 0x959, 0x95a, 0x965, 0x966, 0x969, 0x96a
	.half 0x995, 0x996, 0x999, 0x99a, 0x9a5, 0x9a6, 0x9a9, 0x9aa
	.half 0xa55, 0xa56, 0xa59, 0xa5a, 0xa65, 0xa66, 0xa69, 0xa6a
	.half 0xa95, 0xa96, 0xa99, 0xa9a, 0xaa5, 0xaa6, 0xaa9, 0xaaa

	.text
	.set	noreorder

LEAF(osSetIntMask)
	mfc0	t4,C0_SR
	andi	v0,t4,(SR_IMASK|SR_IE)		
	la      t0, __OSGlobalIntMask           # get global interrupt mask
        lw      t3, 0(t0)
        xor     t0, t3, 0xffffffff
        andi    t0, SR_IMASK
        or      v0, t0                          # subtract __OSGlobalIntMask

	lw	t2, PHYS_TO_K1(MI_INTR_MASK_REG)
	beqz	t2, 1f
	srl     t1, t3,  RCP_IMASKSHIFT
        xor     t1, 0xffffffff
        and     t1, 0x3f
	#lw	k0,__osRunningThread
	#lw	t5, T_CONTEXT_RCP(k0)
	#and	t1, t5
        or      t2, t1                          #subtract __OSGlobalIntMask

1:
	sll	t2, RCP_IMASKSHIFT
	or	v0, t2				# don''t touch v0 any more
	/*
	 * set up RCP interrupt mask.
	 */	
	and	t0, a0, RCP_IMASK
	and	t0, t3
	srl	t0, RCP_IMASKSHIFT-1
	lhu	t2, __osRcpImTable(t0)
	sw	t2, PHYS_TO_K1(MI_INTR_MASK_REG);
	/*
	 * set up SR register.
	 */
	andi	t0, a0,(SR_IMASK|SR_IE)
	andi	t1, t3, SR_IMASK
	and	t0, t1			# merge global and thread IntMask
	and	t4,~SR_IMASK
	or	t4,t0
	mtc0	t4,C0_SR
	nop
	nop
	j	ra
	nop
END(osSetIntMask)