.TH osInvalICache 3P local "Silicon Graphics, Inc."
.SH NAME
.upperok
osInvalICache \- invalidate CPU instruction cache lines
.SH SYNOPSIS
.nf
\f3
.Op c
#include <ultra64.h>
.sp .8v
void osInvalICache(void \(**vaddr, s32 nbytes);
.Op
\f1
.fi
.SH DESCRIPTION
The MIPS R4300 CPU implements a 16 kilobyte direct mapped instruction cache
with a line size of 32 bytes.
The cache is not coherent with respect to physical memory or the data cache and
thus cache lines must be explicitly invalidated when it is desired that
stale instructions not be used when more recent data exists in physical
memory.
The
.I osInvalICache
call invalidates all instruction cache lines that contain the region
.IR  "[vaddr, vaddr + nbytes)" .
The given address
.I vaddr
must be a CPU virtual address,
either direct mapped or mapped via the CPU TLB.
If
.I vaddr
is not aligned to the a cache line boundary,
and
.I nbytes
is not a multiple of the cache line size,
a slightly larger region may be invalidated.
For all practical purposes, this is harmless.
.PP
It is necessary to invalidate the instruction cache when previously executed
instructions are out of date with respect to physical memory.
The situation most commonly occurs when a new code is copied into physical
memory via a direct memory access (DMA) device.
If so,
addresses associated with program text must be invalidated prior to
executing the code at these addresses.
.SH "SEE ALSO"
.IR osMapTLB (3P),
.IR osInvalDCache (3P),
.IR osWritebackDCache (3P),